Tenstorrent Inc
Physical Design SOC Physical Design Lead Santa Clara, California, United States
Tenstorrent Inc, Santa Clara, California, us, 95053
Physical design for high-performance designs going into industry leading CPU and AI/ML architecture. This role involves managing full chip and sub-block floor planning, providing essential collaterals for block-level physical implementation. It includes top-level SoC integration, such as power grid, clocking, and bump planning, while working closely with Architecture, RTL, and packaging teams. The position also drives layout verification closure and owns top-level SoC floorplan methodology and tools.
This role is hybrid, based out of Santa Clara, CA, Austin, TX or Ft. Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities:
Responsible for floor planning of full chip and sub-blocks, delivering floorplan collaterals for block level physical implementation.
Top-level SoC integration including RDL, power grid, clocking and bump planning.
Cross discipline collaboration between Architecture, RTL and packaging teams to drive decisions.
Driving layout verification closure at SoC level.
Drive and own top-level SoC floorplan methodology and tools.
Experience & Qualifications:
Minimum BS and 10+ years of experience in Physical Design of SoCs.
Proven track record of successful tape-outs and meeting performance targets.
In depth practical, hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, routing, DFM techniques and physical verification.
Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor.
Hands-on experience in Power and Signal Integrity analysis.
Ability to debug and fix LVS, DRC, Antenna, ERC issues.
Strong communication and teamwork skills, with the ability to lead and collaborate in a cross-functional environment.
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This role is hybrid, based out of Santa Clara, CA, Austin, TX or Ft. Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities:
Responsible for floor planning of full chip and sub-blocks, delivering floorplan collaterals for block level physical implementation.
Top-level SoC integration including RDL, power grid, clocking and bump planning.
Cross discipline collaboration between Architecture, RTL and packaging teams to drive decisions.
Driving layout verification closure at SoC level.
Drive and own top-level SoC floorplan methodology and tools.
Experience & Qualifications:
Minimum BS and 10+ years of experience in Physical Design of SoCs.
Proven track record of successful tape-outs and meeting performance targets.
In depth practical, hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, routing, DFM techniques and physical verification.
Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor.
Hands-on experience in Power and Signal Integrity analysis.
Ability to debug and fix LVS, DRC, Antenna, ERC issues.
Strong communication and teamwork skills, with the ability to lead and collaborate in a cross-functional environment.
#J-18808-Ljbffr