Qorvo, Inc.
Principal Layout Engineer
Qorvo, Inc., San Jose, California, United States, 95199
Principal Layout Engineer
Job Type: Full-Time
Location: CA - San Jose, US
Requisition ID: 8298
Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves diverse high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense.
Qorvo’s fast-growing Power Management division focusing on Power loss protection, PMICs, Motor Control, and Battery Management solutions for a wide range of Mobile, Consumer, IoT and Industrial applications is looking for an experienced Principal Layout Engineer.
Responsibilities:
Layout of Power and Analog integrated circuits for the general power electronics market (mobile, industrial, consumer)
Floor planning and concept realization of highly integrated analog/power circuits
Top Level and block level layout designs including circuit and layout verification checks (LVS, DRC)
Full Analogue layout design and layout size optimization of CMOS JI and SOI
Interface and cooperation with Analog and Power IC design engineers in Asia and US
Responsibility for tape out process, data documentation and data archiving
Independent interface with design engineering, foundry and manufacturing
Qualifications:
15+ years of relevant work experience
Fluency in Vietnamese preferred.
Background in analog power IC fundamentals and experience with integrated analog mixed-signal circuit layouts
Understanding of semiconductor process technologies like CMOS JI, and SOI
Experience working with voltages in 5-200V range is preferred.
Experience with CAD layout tools like Cadence
Outstanding Analytical and problem-solving skills
Well-developed interpersonal and communication skills
Competitive base salary commensurate with experience: $182,100 - $236,800, relevant for the California Bay Area (subject to change dependent on physical location).
We are an Equal Employment Opportunity (EEO) / Affirmative Action employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, military or veteran status, physical or mental disability, genetic information, and/or any other status protected by law.
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Location: CA - San Jose, US
Requisition ID: 8298
Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves diverse high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense.
Qorvo’s fast-growing Power Management division focusing on Power loss protection, PMICs, Motor Control, and Battery Management solutions for a wide range of Mobile, Consumer, IoT and Industrial applications is looking for an experienced Principal Layout Engineer.
Responsibilities:
Layout of Power and Analog integrated circuits for the general power electronics market (mobile, industrial, consumer)
Floor planning and concept realization of highly integrated analog/power circuits
Top Level and block level layout designs including circuit and layout verification checks (LVS, DRC)
Full Analogue layout design and layout size optimization of CMOS JI and SOI
Interface and cooperation with Analog and Power IC design engineers in Asia and US
Responsibility for tape out process, data documentation and data archiving
Independent interface with design engineering, foundry and manufacturing
Qualifications:
15+ years of relevant work experience
Fluency in Vietnamese preferred.
Background in analog power IC fundamentals and experience with integrated analog mixed-signal circuit layouts
Understanding of semiconductor process technologies like CMOS JI, and SOI
Experience working with voltages in 5-200V range is preferred.
Experience with CAD layout tools like Cadence
Outstanding Analytical and problem-solving skills
Well-developed interpersonal and communication skills
Competitive base salary commensurate with experience: $182,100 - $236,800, relevant for the California Bay Area (subject to change dependent on physical location).
We are an Equal Employment Opportunity (EEO) / Affirmative Action employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, military or veteran status, physical or mental disability, genetic information, and/or any other status protected by law.
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