DFT Lead at Bay Area, CA or Austin, TX) Fulltime

Description: Experience in DFT related tasks Must have a deep understanding of DFT related tasks. Including but not limited to scan insertion, memory BIST, Logic BIST, Serdes and IO test, JTAG, and boundary scan logic features on the chips Deep knowledge of ATE and Functional tests required Knowledge of SRAM, CAM and register file internal circuitry and organization Strong knowledge of logic design techniques RTL/Logic design experience is a plus Verification experience is a plus Timing closure and timing constraints understanding for DFT modes is required Strong communication and interpersonal skills Experience with Perl or other scripting languages is required