ASIC Engineering Technical Leader

The application window is expected to close on 11/30/2024This is an onsite role and will require working out of the Milpitas/San Jose office locationWho We AreThe Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.Who You'll Work WithCome join us and take part in shaping Cisco’s revolutionary solutions for data centers by designing some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world.What You'll DoValidate system architecture and design implementation micro-architecture to ensure final products meet performance expectations.Gather information from underlying system specifications and ask detailed probing questions as needed to construct accurate and efficient models.Partition overall systems to be modeled into lower level blocks while keeping modularity, re-use, and test requirements in mind.Construct OMNeT++ models for underlying blocks that will stitch together to form the overall target system to be validated.Define and execute test plans to validate system performance goals.Compile test results, summarize important findings, rationalize any unexpected observations, and offer insights on how to improve performance.Minimum Qualifications:Bachelor’s or Master’s degree with 8+ years of hands-on experience with ASIC micro-architecture or modeling.Prior experience with C++ programming and debugging complex programs.Prior experience with network switch fabric concepts, queuing, scheduling, buffer management, congestion handling, etc.Prior experience building test benches from scratch, hands-on experience with System Verilog constraints, structures, and classes.Prior experience with cross-functional teams and possess the drive to learn and grow.Preferred Qualifications:Experience with modeling systems and network switches, particularly with OMNeT++ would be a plus.Domain experience on one or more protocols – PCIe, Ethernet, RDMA, TCP.We Are Cisco#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here’s how we do it. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (30 years strong!) and only about hardware, but we’re also a software company. And a security company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns, and protects. No other company can do what we do – you can’t put us in a box! But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.) Day to day, we focus on the give and take. We give our best, we give our egos a break, and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward.

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