ASIC Engineering Technical Leader

Cisco Silicon One (#CiscoSiliconOne) brings together networking, compute, and storage all in a single system. Come join us and take part in shaping Cisco’s revolutionary solutions by designing, developing, and testing some of the most complex ASICs being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, Security, etc.). Our Hardware and Software solutions are tightly coupled with the development cycles that give us an unparalleled advantage in enabling our customers to adopt the latest what technology can offer. As part of Cisco Silicon One (#CiscoSiliconOne), our team develops complex, high-performance, feature-rich ASICs used in Cisco's networking products and third-party custom-built hardware solutions.What You'll DoBe part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL Design.Create micro-architecture specifications and participate in reviews.Implement Verilog RTL to meet timing and performance requirements.Help define, evolve, and support our design methodology.Collaborate with the verification team on an as-needed basis to address design bugs and close code coverage.Work closely with the physical design team to close design timing and place-and-route issues.Triage, debug, and root cause simulation, software bring-up, and customer failures.Perform diagnostic and post-silicon validation tests in the lab.Who You'll Work WithYou will work with front-end RTL Design and Verification teams and Architects to understand chip architecture. You’ll work with SDK and Software teams as part of ASIC development to create a seamless handshake between hardware and software functionalities and qualify use-case requirements. You’ll also work with systems-testing teams as part of post-silicon validation efforts to bring-up, debug, and qualify the ASIC in deployment-mode applications.Minimum Qualifications:Bachelor's or a Master’s Degree in Electrical or Computer Engineering, with 10+ years of related work experience.Prior experience with developing Micro-Architecture for blocks.Prior experience with Verilog/System Verilog.Prior experience with Clock Domain, Reset Domain Crossing issues, and Low-Power Design Techniques.Prior experience with simulators and waveform debugging tools.Prior experience working with Linting, Synthesis, and Static Timing Analysis tools.Prior experience with Verification methodologies including experience developing testbenches, writing System Verilog Assertions, and debugging Netlist simulations.Preferred Qualifications:Understanding of Networking technologies and concepts.Experience with ARM protocols (AXI, CHI, APB, AHB) and exposure to ARM CPUs is desirable.Design experience with Ethernet MAC, DDR/LPDDR, PCIE, and DMA controllers is a plus.Experience with Integrating 3rd party IPs into SoC is desirable.Scripting experience (Python, Perl, TCL, shell programming) highly desirable.Experience with Emulation and Formal Verification tools is a plus.We Are Cisco#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their businesses. Cisco is at the vanguard of impact: delivering our technology in meaningful ways allowing people to live more fulfilling and richer lives. We are a culture that allows for innovation, creativity, and yes, even failure (if you learn from it).Message to applicants applying to work in the U.S. and/or Canada:When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits.

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