Qorvo, Inc.
Digital IC Design Engineer - Power Management
Qorvo, Inc., Bloomington, Minnesota, United States,
Experience Level: Recent College GradJob Type: Full-TimeLocation: MN - Bloomington, USRequisition ID: 8321Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves diverse high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit
www.qorvo.com
to learn how our diverse and innovative team is helping connect, protect and power our planet.Summary:
Qorvo is seeking a Digital Design Engineer responsible for a wide variety of Digital ASIC Design tasks. Designs primarily interface to Analog Power Solutions, including development of State Machines, Serial Interfaces, Register Blocks, OTP Blocks, supporting Clock and Reset analog circuits, and timed enabling/switching of Analog signal paths. This position involves the full Digital Design flow including interacting with Systems for Specification generation, Architecture development, RTL description using System Verilog, Verilog Simulation Verification via developed Test Benches, Logic Synthesis, executing a Place & Route tool and associated Static Timing Analysis, and familiarization with Scan testing. Documentation and presentation at Design Reviews is required.Responsibilities:
Receive Specifications from Module Architects/System Engineers – review, assess, provide feedback, and develop a digital micro-architectureGenerate RTL to comply with specifications, both by manual development and automated generationCreate Cadence schematic database of Digital Blocks via VirtuosoSystem Verilog Verification Simulations of the design by creating Test Benches at block level. Create new Verification tests and utilize existing tests that are to be modified as needed. Execute both RTL and Gate Simulations.Execute Logic SynthesisCreate DFT hooks and generate test patternsExecute remaining back-end tools – Place & Route/Static Timing Analysis, LEC, LINT, CDC, ATPGQualifications:
System Verilog / Verilog Language and SimulationScripting languages (Python, TCL, UNIX/LINUX, shell, PERL, C/C++)Synthesis and Static Timing AnalysisStrong communication skills to interface with other teamsBSEE required, MSEE preferredPlace & Route using Cadence Virtuoso, verifying Database vs SchematicsSystem Verilog Assertions and Functional CoverageMAKE A DIFFERENCE AT QORVOWe are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.We are an Equal Employment Opportunity (EEO) / Affirmative Action employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, military or veteran status, physical or mental disability, genetic information, and/or any other status protected by law.
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www.qorvo.com
to learn how our diverse and innovative team is helping connect, protect and power our planet.Summary:
Qorvo is seeking a Digital Design Engineer responsible for a wide variety of Digital ASIC Design tasks. Designs primarily interface to Analog Power Solutions, including development of State Machines, Serial Interfaces, Register Blocks, OTP Blocks, supporting Clock and Reset analog circuits, and timed enabling/switching of Analog signal paths. This position involves the full Digital Design flow including interacting with Systems for Specification generation, Architecture development, RTL description using System Verilog, Verilog Simulation Verification via developed Test Benches, Logic Synthesis, executing a Place & Route tool and associated Static Timing Analysis, and familiarization with Scan testing. Documentation and presentation at Design Reviews is required.Responsibilities:
Receive Specifications from Module Architects/System Engineers – review, assess, provide feedback, and develop a digital micro-architectureGenerate RTL to comply with specifications, both by manual development and automated generationCreate Cadence schematic database of Digital Blocks via VirtuosoSystem Verilog Verification Simulations of the design by creating Test Benches at block level. Create new Verification tests and utilize existing tests that are to be modified as needed. Execute both RTL and Gate Simulations.Execute Logic SynthesisCreate DFT hooks and generate test patternsExecute remaining back-end tools – Place & Route/Static Timing Analysis, LEC, LINT, CDC, ATPGQualifications:
System Verilog / Verilog Language and SimulationScripting languages (Python, TCL, UNIX/LINUX, shell, PERL, C/C++)Synthesis and Static Timing AnalysisStrong communication skills to interface with other teamsBSEE required, MSEE preferredPlace & Route using Cadence Virtuoso, verifying Database vs SchematicsSystem Verilog Assertions and Functional CoverageMAKE A DIFFERENCE AT QORVOWe are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.We are an Equal Employment Opportunity (EEO) / Affirmative Action employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, military or veteran status, physical or mental disability, genetic information, and/or any other status protected by law.
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