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Renesas Electronics Corporation

Staff DFT Engineer

Renesas Electronics Corporation, Indiana, Pennsylvania, us, 15705


Renesas is looking for a technical leader to drive the DFT aspects of high-performance compute SOC/MCU development. The candidate must be experienced, hands-on and have robust understanding of testability features including SSN, MBIST, LBIST, Scan Insertion, ATPG, GLS and post silicon debug on automotive grade SOCs.

Responsibilities

Handling large scale SOC for hierarchical scan insertion and SSN based ATPG flow.

Integration and Verification of MBIST at RTL level.

RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST.

Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards.

Post silicon debug activities for DFT patterns.

Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role.

Qualifications

Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science

At least 8 years of experience in related domains and have working knowledge of industry standard digital EDA toolkits.

Must be conversant on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc

Strong scripting skills for Automation and Flow development using PERL/TCL/Python.

Can – do attitude, openness to new environment, people and culture

Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus.

Ability to work independently and as part of a team.

Mentor and guide junior engineers in DFT.

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