Faraday Technology Corporation
Senior SERDES circuit Design – Analog & Mixed signal
Faraday Technology Corporation, Oregon, Illinois, United States, 61061
Requirements
MS plus 3 years or BS plus 6 years of minimum relevant experience or Ph.D in relevant fields.
Experience in at least one of the following areas is a must:
SerDes receiver circuit design, including CTLE, DFE, CDR, deserializer.
SerDes transmitter design, clock buffer distribution, TX driver, serializer.
SerDes clocking design, PLL, LCVCO, DLL, phase interpolator, duty cycle correction circuit design.
Receiver adaptation, channel simulation, IBIS model, SERDES protocol such as PCIe/USB/SATA/Ethernet/PON (OLT, ONU).
Skills
Hands-on analog building block design/layout & debug experience.
Hands-on experience in silicon test and debug.
Familiar with SerDes system operation.
Familiar with SerDes architecture definition & system modeling/analysis.
Familiar with SerDes protocols such as PCIe, USB, SATA, 802.3 Ethernet, etc.
Basic knowledge on SerDes PCS/controller design.
Basic knowledge on high-speed package and board design.
Familiar with both analog & mixed signal design flow & tools.
Familiar with Verilog, Verilog-A/AMS, Matlab.
Highly self-disciplined and motivated with strong integrity.
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MS plus 3 years or BS plus 6 years of minimum relevant experience or Ph.D in relevant fields.
Experience in at least one of the following areas is a must:
SerDes receiver circuit design, including CTLE, DFE, CDR, deserializer.
SerDes transmitter design, clock buffer distribution, TX driver, serializer.
SerDes clocking design, PLL, LCVCO, DLL, phase interpolator, duty cycle correction circuit design.
Receiver adaptation, channel simulation, IBIS model, SERDES protocol such as PCIe/USB/SATA/Ethernet/PON (OLT, ONU).
Skills
Hands-on analog building block design/layout & debug experience.
Hands-on experience in silicon test and debug.
Familiar with SerDes system operation.
Familiar with SerDes architecture definition & system modeling/analysis.
Familiar with SerDes protocols such as PCIe, USB, SATA, 802.3 Ethernet, etc.
Basic knowledge on SerDes PCS/controller design.
Basic knowledge on high-speed package and board design.
Familiar with both analog & mixed signal design flow & tools.
Familiar with Verilog, Verilog-A/AMS, Matlab.
Highly self-disciplined and motivated with strong integrity.
#J-18808-Ljbffr