Apple
Graphics FE Implementation Engineer
Apple, Orlando, Florida, us, 32885
Graphics FE Implementation Engineer
Orlando, Florida, United States
Hardware
Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Engineering group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processors! You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. As part of the GPU FE Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day!
Description
The successful candidate will work closely with the RTL and PD (physical design) teams and be responsible for synthesis, analysis, and optimization of the delivered IP. For this role, use and develop advanced techniques to meet challenging timing, power, and area targets while also working with our partners in STA and DFT to achieve successful first silicon. Through this collaboration, you will deliver the best-in-class GPUs for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.
Minimum Qualifications
Key Qualifications
We seek highly motivated individuals with expert synthesis design experience that understand RTL design principles and can drive quality physical design implementation.
Own block level synthesis and drive analysis and optimizations using advanced synthesis techniques and RTL design improvement for optimal Area, Timing, and Power.
Collaborate with Physical Design and Timing Analysis teams on physical concepts like floor-planning, placement, congestion, and timing constraints.
Analyze architectural critical paths and drive multi-block closure across RTL Design and Physical Design teams.
Debug complex logic equivalence issues and review netlist checks to validate functionality and netlist quality.
Demonstrated ability to solve complex problems across multiple technical domains.
Develop and drive adoption of innovative methodologies across projects and teams.
Experience implementing ECOs for functionality and timing.
Experience with one or more of: reset domain, multi-clock domain, multi-power domain (UPF), linting tools across RTL and Gate-Level.
Relevant scripting experience in ASIC flows – python, tcl, Perl, Data manipulation.
Preferred, but not required:
Familiarity with DFT insertion.
Familiarity with simulation, debugging tools, and experience of working closely with the design verification team.
Experience working on GPUs is desirable.
Preferred Qualifications
Education & Experience
We are looking for candidates with BS + 10 years of relevant experience.
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Orlando, Florida, United States
Hardware
Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Engineering group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processors! You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. As part of the GPU FE Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day!
Description
The successful candidate will work closely with the RTL and PD (physical design) teams and be responsible for synthesis, analysis, and optimization of the delivered IP. For this role, use and develop advanced techniques to meet challenging timing, power, and area targets while also working with our partners in STA and DFT to achieve successful first silicon. Through this collaboration, you will deliver the best-in-class GPUs for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.
Minimum Qualifications
Key Qualifications
We seek highly motivated individuals with expert synthesis design experience that understand RTL design principles and can drive quality physical design implementation.
Own block level synthesis and drive analysis and optimizations using advanced synthesis techniques and RTL design improvement for optimal Area, Timing, and Power.
Collaborate with Physical Design and Timing Analysis teams on physical concepts like floor-planning, placement, congestion, and timing constraints.
Analyze architectural critical paths and drive multi-block closure across RTL Design and Physical Design teams.
Debug complex logic equivalence issues and review netlist checks to validate functionality and netlist quality.
Demonstrated ability to solve complex problems across multiple technical domains.
Develop and drive adoption of innovative methodologies across projects and teams.
Experience implementing ECOs for functionality and timing.
Experience with one or more of: reset domain, multi-clock domain, multi-power domain (UPF), linting tools across RTL and Gate-Level.
Relevant scripting experience in ASIC flows – python, tcl, Perl, Data manipulation.
Preferred, but not required:
Familiarity with DFT insertion.
Familiarity with simulation, debugging tools, and experience of working closely with the design verification team.
Experience working on GPUs is desirable.
Preferred Qualifications
Education & Experience
We are looking for candidates with BS + 10 years of relevant experience.
#J-18808-Ljbffr