Design Verification Engineer

Design Verification Engineering :7 to 15 Years

Work Location : Sunnyvale , CA

Testbench development – System Verilog Universal Methodology (“UVM”), Python, and C tests

Integration/development of C tests/Application Programming Interface (“APIs”) and software build flow

Integration of UVM testbenches

• Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements
• Continuous integration and/or regression testing setup and debug for simulation at both RTL and Gate Level Netlist
• Unified Power Format (“UPF”) power aware simulation/emulation.
• XProp simulation/regression TestBench creation and maintenance .Coverage collection and closure
• Documentation of tests, testbench, use-cases, exclusions, and status