Design Verification Engineer

Project Description:

• We are looking for a seasoned UVM Developer to lead our efforts in creating robust verification environments for complex semiconductor devices. This role demands deep expertise in using cutting-edge simulation tools, primarily Xcelium, to drive functional simulations and comprehensive documentation. The successful candidate will play a pivotal role in enhancing our product reliability and accelerating our time-to-market.

Responsibilities:

• • Develop and maintain UVM test benches for advanced verification of digital designs
• • Utilize simulation tools such as Xcelium to perform functional simulations, ensuring design integrity and performance
• • Optimize existing verification environments to improve efficiency and effectiveness of simulations
• • Work closely with design and system engineering teams to understand requirements and implement verification strategies accordingly
• • Analyze simulation results, identify and troubleshoot discrepancies to ensure product specifications are met
• • Document verification processes and results thoroughly to support design validation and future references

Mandatory Skills Description:

• • Proven expertise in Universal Verification Methodology (UVM) for creating and managing test benches
• • Proficiency with simulation tools like Xcelium or similar environments for functional simulation of digital designs
• • Strong analytical skills to interpret complex design specifications and simulation results
• • Excellent problem-solving abilities, with a keen attention to detail in troubleshooting and optimizing verification environments

• Nice-to-Have Skills Description:
• • Experience with other verification languages and methodologies such as SystemVerilog, OVM, or VMM
• • Familiarity with ASIC design flow and constraints
• • Prior experience in the semiconductor or electronics manufacturing industries