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Palo Alto Networks

Post Silicon Validation Engineer LPDDR5 - Contractor - Palo Alto Networks [Contr

Palo Alto Networks, Santa Clara, CA, United States


This role is a contract assignment at Palo Alto Networks. Contractors will not be employed by Palo Alto Networks but through our trusted staffing partners.

Palo Alto Networks is looking for a Post Silicon Validation Engineer LPDDR5 - Contractor to work with the ASIC team and is a great opportunity for a talented individual who has the desire to associate with a fast-growing company in a truly international environment.

  • Location - Santa Clara, CA (Hybrid)
  • Duration - 6 months

As a Post Silicon Validation Engineer LPDDR5 (Contractor) you will directly and visibly contribute to our overall success and daily operations within the ASIC team. In this role, you will be performing validation of the different components of our current ASIC. The role requires familiarity with ASIC validation, lab bring-up, scripting and using scopes and analyzers.

This role is pivotal to the success of the organization, is collaborative in nature, and will continue to flex and grow as the organization matures. If you are a self-starter who thrives in fast-paced, high-growth environments with minimal supervision this is the role for you!

Your Impact

  • Develop and run post-silicon validation tests and associated scripts for successfully validating the LPDDR5 interface in a multi-chip module.
  • Analyze and debug test failures independently to identify root cause.
  • Debug complex cross-functional issues with ASIC, system hardware, and software engineers.
  • Build powerful programs in Python and C to automate testing, regression, and debugging.

Your Experience

  • 5+ years of relevant post-silicon validation experience.
  • Proficiency with lab equipment, logic analyzers, and oscilloscopes.
  • Expertise in Python and C.
  • Thorough understanding of DDR standards (e.g. JEDEC) and technologies.
  • Proven success in functional and electrical bring-up and validation of DDR interfaces on multiple ASICs.
  • Familiarity with signal integrity for LPDDR4/5 interfaces is preferred.
  • Demonstrated ownership and independence in planning, analyzing, debugging, driving vendors, and reporting status.
  • Strong collaboration and communication skills.

Education

BS or MS in Electrical Engineering, Computer Engineering, Computer Science or equivalent experience.

Our Team

Our ASIC team has an opportunity like no other industry: high impact work and the chance to change the future of digital security. This team builds ASICs for our industry-leading Next Gen Firewall. Being part of the ASIC team at Palo Alto Networks means that you will be in the midst of the changes impacting our industry, and helping our internal teams, customers, and partners address the ever-changing threats we all face on a day-to-day basis.

Compensation

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer, this is the pay range that Magnit (the staffing agency) reasonably expects to pay for this position: $120/hour to $130/hour. Please note that the compensation information in this posting reflects the hourly wage only and does not include benefits. Magnit offers Medical, Dental, Vision and 401K.

Information about Palo Alto Networks

At Palo Alto Networks®, everything starts and ends with our mission:

Being the cybersecurity partner of choice, protecting our digital way of life.

We have the vision of a world where each day is safer and more secure than the one before. These aren’t easy goals to accomplish — but we’re not here for easy. We’re here for better. We are a company built on the foundation of challenging and disrupting the way things are done, and we’re looking for innovators who are as committed to shaping the future of cybersecurity as we are.