NVIDIA Corporation
Senior ASIC Floorplan Design Engineer
NVIDIA Corporation, Santa Clara, California, us, 95053
Senior ASIC Floorplan Design Engineer
We are now looking for a Senior ASIC Floorplan Design Engineer!NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.What you will be doing:Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.You will build tools and improve existing infrastructure to optimize chip area and speed of execution.What we need to see:Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.6+ years of relevant work experience.A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.Experience in Verilog, System Verilog or similar HVL.Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.Python, Perl and C/C++ programming language experience.Ways to stand out from the crowd:Experience in driving development of large scale ASIC floorplan is a huge plus.NVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.The base salary range is 164,000 USD - 356,500 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for equity and benefits.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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We are now looking for a Senior ASIC Floorplan Design Engineer!NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.What you will be doing:Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.You will build tools and improve existing infrastructure to optimize chip area and speed of execution.What we need to see:Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.6+ years of relevant work experience.A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.Experience in Verilog, System Verilog or similar HVL.Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.Python, Perl and C/C++ programming language experience.Ways to stand out from the crowd:Experience in driving development of large scale ASIC floorplan is a huge plus.NVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.The base salary range is 164,000 USD - 356,500 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for equity and benefits.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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