Physical Design Engineer

The application window is expected to close on 11/30/2024. This is an onsite role and will require working out of the Milpitas/San Jose office location. Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do You will be part of ASIC physical design Team which is responsible for full Chip physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities will include: Perform full chip DRC/LVS/ERC/ANT checks, review and debug the issues, provide solutions and ensure signoff clean results. Work with block and top level implementation teams to understand physical aspects and feedback on necessary updates. Work closely with block and TOP level physical implementation, IP development teams to resolve PV issues and address to proper owners. Deploy and improve physical verification flows and methodologies. Develop custom check as per need for verification robustness. Support block and TOP implementation teams to solve local PV issues. Minimum Qualifications: BS/MS in Electrical Engineering or Computer Science, with 7+ year minimum of hands-on experience in ASIC implementation and Physical verification. Prior experience with physical verification (DRC, LVS, ERC, ANT), debug and solution. Prior experience in one of the scripting languages (Python, Tcl, Skill). Preferred Qualifications: Tapeout Experience on 7nm nodes and below. Prior experience working with semiconductor foundries on installation, and maintenance of process design kits (PDKs) for SOC physical design teams. 7+ years of experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support. Previous work experience working with Package and floorplan teams to define padring and bump-map design. Background in industry-standard physical verification EDA tools. Why Cisco #WeAreCisco - We connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren't afraid to change the way the world works, lives, plays and learns. We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers.

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