Goertek Electronics
Senior Layout Team Lead
Goertek Electronics, Seattle, Washington, United States, 98101
Summary
We are seeking a Senior Layout Team Leader at GoerTek Santa Clara office to work on consumer electronics optical products. The Senior Layout Team Leader serves as the primary technical point of contact and in-house expert for a wide range of products and acts as the interface between the company and its customers. The Senior Layout Team Leader will guide the layout design process, work with our factory R&D team, production engineering, and other teams to introduce new products, improve design performance, and solve layout related issues arising in production. This job description reflects management’s assignment of essential functions, other duties may be assigned.
Key Responsibilities
Collaborate with customers to arrange the design schedule, review the design status, summary the layout feedback for all designs, reply the DFM items from the PCB vendor.Collaborate with customers and PCB vendor to get the suitable stack up for the new design.Undertake the layout design tasks from customers daily and pass the tasks to the internal team.Take responsibility to transfer schematic netlist/MCO into the PCB design, layout design including placement and routing, review the layout design, and output the Gerber files.Communicate with customer on a regular basis to get the new technical road map of PCB design for the new project; help the company to introduce new related electronic products solution and assist R&D team to secure key design win projects.
Qualifications
Master’s degree in the Electrical Engineering field.5+ years of experience in layout design experience in electronic product layout design, completed 10layers of HDI board independently.Experience with Cadence Allegro at least 3 years of experience in constraint manager/design rules.Deep understanding on electronic circuits and rich experiences in high-speed design, familiar with PISI simulation , master the design rules, familiar with the EMC/EMI, and experience in Qualcomm chips design is preferred.Proficient with both rigid board and flex board design, understand the PCB/flex fab process, and communicates with the DFM with vendor directly.Proficient with DFM/DFA, identifying the risks in the Layout design, work with PD/EE/DFx team on improving the design.Good communication skills and team player.Fluent in conversational Mandarin is highly desired.Travel at our HQ office at our customers’ request.The base pay range for this role is between $127,000.00 to $177,000.00 annually and your base pay will depend on your skills, qualifications, experience, and location.
We are seeking a Senior Layout Team Leader at GoerTek Santa Clara office to work on consumer electronics optical products. The Senior Layout Team Leader serves as the primary technical point of contact and in-house expert for a wide range of products and acts as the interface between the company and its customers. The Senior Layout Team Leader will guide the layout design process, work with our factory R&D team, production engineering, and other teams to introduce new products, improve design performance, and solve layout related issues arising in production. This job description reflects management’s assignment of essential functions, other duties may be assigned.
Key Responsibilities
Collaborate with customers to arrange the design schedule, review the design status, summary the layout feedback for all designs, reply the DFM items from the PCB vendor.Collaborate with customers and PCB vendor to get the suitable stack up for the new design.Undertake the layout design tasks from customers daily and pass the tasks to the internal team.Take responsibility to transfer schematic netlist/MCO into the PCB design, layout design including placement and routing, review the layout design, and output the Gerber files.Communicate with customer on a regular basis to get the new technical road map of PCB design for the new project; help the company to introduce new related electronic products solution and assist R&D team to secure key design win projects.
Qualifications
Master’s degree in the Electrical Engineering field.5+ years of experience in layout design experience in electronic product layout design, completed 10layers of HDI board independently.Experience with Cadence Allegro at least 3 years of experience in constraint manager/design rules.Deep understanding on electronic circuits and rich experiences in high-speed design, familiar with PISI simulation , master the design rules, familiar with the EMC/EMI, and experience in Qualcomm chips design is preferred.Proficient with both rigid board and flex board design, understand the PCB/flex fab process, and communicates with the DFM with vendor directly.Proficient with DFM/DFA, identifying the risks in the Layout design, work with PD/EE/DFx team on improving the design.Good communication skills and team player.Fluent in conversational Mandarin is highly desired.Travel at our HQ office at our customers’ request.The base pay range for this role is between $127,000.00 to $177,000.00 annually and your base pay will depend on your skills, qualifications, experience, and location.