ASIC DFT Technical Program Manager

The application window is expected to close by 12/20/2024.This is an onsite role and will require working out of the Milpitas/San Jose office location.Who We AreThe Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing, and testing some of the most complex ASICs being developed in the industry.What You'll DoWork closely with DFT architecting leads to define and the DFT implementation specifications.Responsible for closely managing the DFT implementation execution schedules, tracking status, dependencies, and deliverable commitments.Responsible for creating (collaborating with the team) and maintaining DFT checklist for different design phases, to ensure good quality.The job requires the candidate to have the ability to collect and present and track DFT implementation status in an organized and easy to track manner.Who You'll Work WithYou will be in the Silicon One development organization as an ASIC DFT Technical Program Manager in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team, you will also be involved in crafting groundbreaking next-generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.Who You AreMinimum Qualifications:Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 8 years of experience.Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.Prior experience working with Gate level simulation, debugging with VCS and other simulators.Prior experience with Scripting skills: Tcl, Python/Perl.Preferred Qualifications:Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687.Prior experience with full chip DFT architecture, hierarchical testing, and high-speed interface testing.We Are Cisco#WeAreCisco. We are all unique, but collectively we bring our talents to work as a team, to develop innovative technology and power a more inclusive, digital future for everyone. How do we do it? Well, for starters – with people like you!

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