Senior Deep Learning Compiler Engineer (GPU)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role IREE is an open source, MLIR based, compilation stack that supports compilation of ML models on multiple target architectures. For many of these architectures, like x86, ARM, RISC-V, as well as some APUs, LLVM compilation is the last layer of the compilation stack. In this role, the candidate will be expected to enhance the LLVM compilation on current and future AMD GPUs. The role is expected to be central to be able to achieve good performance on various LLVM based GPU backends using IREE and will have a direct impact on effective deployment of ML models on AMD devices. The person This role is ideal for someone who has experience with LLVM; knows/is interested in learning the best way to achieve good performance on given architecture. This person must be able to understand the current MLIR/LLVM based compilation flow, to effectively identify opportunities for optimization at various levels of the stack. They must be able to design and implement these optimizations either in LLVM or in MLIR, to optimize the binary generated by the compiler. The person must also enjoy working in open-source projects like MLIR, LLVM and IREE and be able to engage with the community effectively. This role is ideal for someone who might be new to MLIR but is interested in contributing to it. Key responsibilities Support and contribute to AMD GPU backend compilation in LLVM. Understand current and upcoming architecture features on AMD GPUs and help design the compiler strategy to target these features effectively within IREE. Plan for and design compiler transformations in MLIR or LLVM that are needed to generate efficient code. Contribute to and engage with open-source communities in LLVM, MLIR and IREE. Maintain high level of code quality and testing. Preferred experience Bachelor's, Master's or PhD in computer science or related field. Multiple years of experience working with an LLVM based compiler, MLIR experience optional Known history of contribution to open-source projects is preferred Prior experience in ML compilers is optional but preferred. Experience with fuzzers and reducers is a plus. Location San Jose / Seattle LI-G11 LI-HYBRID At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD's Employee Stock Purchase Plan. You'll also be eligible for competitive benefits described in more detail here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.