Test Timing Engineer

Meet the TeamThe Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed.Your ImpactYou are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate effectively with cross-functional teams, communicate complex timing data clearly, and are always focused on driving designs to closure. Responsibilities will include: Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs.Check timing for unconstrained endpoints, no clock, etc. Your role may include SDC validation, CDC delay check, and SDC flow development. STA runs, more specifically at scan modes along with advising the Physical Design team on best practices. Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.Minimum QualificationsBachelor’s degree in electrical or computer engineering (or other equivalent field) with 8+ years of related work experience.Experience with block/full chip SDC development in test modes (scan shift, scan capture, atpg capture modes).Expertise in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus.Programming skills in at least 2 or more of the following languages: Perl, TCL, Python, Makefile, or other relative scripting languages. Preferred QualificationsMaster’s Degree in electrical or computer engineering (or other equivalent field) with 6+ years of related work experience.Thorough understanding of noise, cross talk, OCV, Sigma effects and Liberty file formats including standard cells/memory/IO/IP modeling and its usage in the ASIC flow.Background in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.Prior working experience with SDC debugging & STA tools: Synopsys GCA/TCM/Primetime, Cadence CCD/Tempus.Strong communication skills and team player. Why Cisco#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re "old" (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can’t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us! #WeAreCiscoLocation:San Jose, California, USArea of InterestEngineer - HardwareCompensation Range149600 USD - 214100 USD Job TypeProfessionalTechnology Interest*NoneJob Id1431102Message to applicants applying to work in the U.S. and/or Canada:When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process.U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday, plus a day off for their birthday. Employees accrue up to 20 days of Paid Time Off (PTO) each year and have access to paid time away to deal with critical or emergency issues without tapping into their PTO. We offer additional paid time to volunteer and give back to the community. Employees are also able to purchase company stock through our Employee Stock Purchase Program.Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows:.75% of incentive target for each 1% of revenue attainment up to 50% of quota;1.5% of incentive target for each 1% of attainment between 50% and 75%;1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.