Esperanto.ai
SR PERIPHERAL SUBSYSTEM DESIGN ENGINEER
Esperanto.ai, Portland, OR
Description
We are looking for a candidate to join our next generation Systems on a Chip (SOC) RTL design team. The candidate will be a part of the I/O design team responsible for specifying, implementing and integrating Verilog RTL IPs into our custom high performance, energy efficient AI processor.
Responsibilities
Qualifications
Additional Success Factors
Benefits
We are looking for a candidate to join our next generation Systems on a Chip (SOC) RTL design team. The candidate will be a part of the I/O design team responsible for specifying, implementing and integrating Verilog RTL IPs into our custom high performance, energy efficient AI processor.
Responsibilities
- Integrate 3rd party vendor's Verilog IP into standard bus protocols
- Write microarchitecture specifications
- Work with design verification team to draft test plans, debug test failures and to ensure functional correctness
- Synthesize RTL to logic gates using standard CAD tools and build timing and area constraints
- Interact closely with physical design team to guarantee proper backend implementation
- Support Silicon bringup and diagnostics
- Evaluate potential new vendor's I/O IP for use in next generation design
Qualifications
- BS in EE or related technical field
- +5 years in ASIC/SOC design and Verilog RTL coding experience
- Completed ASIC/SOC design projects with successful tapeouts
- Experience in industrial standard ASIC/SOC CAD tools for simulation, synthesis, debug, timing analysis and power estimation
- Experience with PCIe Controller and PHY IPs
- Experience with AXI interface
- Excellent verbal and written communication skills
Additional Success Factors
- Knowledge of I/O protocols such as SMBus, PCI Express, UART
- Previous projects using Synopsys CAD tools
- Experience in ASIC/SOC designs with multiple power and clock domains, and integrating UPF into design flow
- Experience in low-power SOC design
- Knowledge of scripting and automation in Linux environment
- Strong planning, organizational, problem solving and analytical skill set; supported by critical thinking and attention to details, and be able to negotiate, assert and communicate effectively.
- A team player in a chip design startup environment who is able to interact with sites in different geographical locations and time zones.
Benefits
- Base salary range is $100,000 - $300,000
- The actual salary of a successful applicant may vary from the posted range based on a candidate's experience, training, education, location and/or other legitimate business reasons.
- You will also be eligible for stock options and benefits.