Senior RTL Analysis Methodology Engineer

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.We are looking for a motivated CAD Methodology Engineer to join our dynamic and growing team. If you like solving challenging problems in asynchronous digital design and verification in a highly multi-functional work environment then join us today! Be part of a diverse team creating NVIDIA's chip design methodology! We're responsible for the RTL CDC and RDC methodology for all of NVIDIA's semiconductor products.What you'll be doing:You will be part of NVIDIA's RTL analysis CAD team, responsible for developing flows, methodology, and application support for Clock Domain Crossing(CDC), Reset Domain Crossing(RDC).Employ good software engineering practices to develop leading-edge CAD flow for EDA tools like (but not limited to) Meridian.Evaluate, deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis.Serve as an in-house EDA tools specialist. Act as liaison between designers and EDA vendors. Analyze issues, build solutions or workarounds, and provide test cases to EDA vendors.Invent new methodologies to improve coverage and user efficiency by employing new tools, and automation including AI.Write technical documents and train internal users.Set up and maintain flow regressions and QA.Employ data collection, analysis, and reporting tools to acquire methodology insights.What we need to see:BS or MS in Electrical Engineering, Computer Engineering, or related fields (or equivalent experience). BS with 6+ years, or MS with 4+ years of experience in RTL analysis, RTL design, and verification.Deep understanding of static sign-off technologies CDC, RDC and Formal.Proficiency in one or more scripting languages (eg: Perl, Python, Tcl) and Make.Proficiency in Verilog SystemVerilog HDL.Excellent problem solving and debugging skills.Strong interpersonal and collaboration skills are required.Ways to stand out from the crowd:Hands-on experience with commercially available RTL analysis tools like Meridian CDC/RDC, Spyglass CDC, or VC CDC.Hands-on experience in digital design of asynchronous interfaces.Familiarity with Machine Learning/Deep Learning.NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.The base salary range is 128,000 USD - 258,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.You will also be eligible for equity and benefits. NVIDIA accepts applications on an ongoing basis. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa ClaraType: Full time