Digital Design Methodology Engineer

Digital Design Methodology Engineer Cupertino, California, United States Hardware Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. Description As a team member of the Methodology Design team, you will be involved with all aspects of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Provide innovative solutions to customize and improve quality and efficiency of mixed-signal design. Work with RTL and physical design teams to implement and customize design flows that are optimal for different IPs. Provide documentation, training, and new-user support. Responsible for diagnosis, resolution, regression of reported problems. Generate block/chip level static timing constraints. Create full chip floor-plan including pin placement, partitions, and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area, and power constraints. Generate and implement ECOs to fix timing, noise, and EM IR violations. Run physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing design methodologies for correct by construction designs. Assist in flow development for chip integration. Minimum Qualifications BS degree in technical discipline with minimum 3 years of relevant experience. Key Qualifications Preferred Qualifications Typically requires 4+ years experience in Synthesis, PNR and Power/Timing flows development. Understanding and exposure to Low Power Design analysis flows. Understand various aspects of partition level Synthesis and PNR including Power/Timing optimization, CTS, routing, and UPF. Understand hierarchical Synthesis and P&R issues is key (UPF, power-distribution, multi-voltage design). Strong TCL/Perl/Python/Makefile scripting knowledge. Proven track record of managing and regressing Synthesis, P&R and Power/timing flows. Self-motivated, dedicated problem solver with strong interpersonal/communication skills. Pay & Benefits At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100 and $264,200, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. You’ll also receive benefits including comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and reimbursement for certain educational expenses related to advancing your career at Apple. Equal Opportunity Employer Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.

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