Veear

Senior Memory Design Engineer

Veear, Austin, TX, United States

Key Qualifications

The ideal candidate will have 10 years of custom circuit design experience from RTL-GDS for CPU and SoC applications
Prior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cells
Experience designing transistor-level custom circuits in advanced FinFET technology nodes Must have a solid experience with the custom circuit tool flows for delivering design collaterals.
A solid understanding of device physics, process technology and circuit design techniques for high performance, low power
Experience with advanced process design rules and supervising mask design
Knowledge developing automation for compilers and standard cells
Post-Silicon test and debug experience
Ability to work well in a team and be productive under aggressive schedules.
Excellent problem solving, written and verbal communication

Responsibilities :

Drive design and development of SRAM, register file, custom cells to enable high performance and low power designs
Work with microarchitecture team to gather specifications and drive optimal implementation
Conduct early sizing estimates and PPA analysis . Design entry and simulations for optimal design sizing.
Design equivalence checking using the latest industry standard LEC tools
Work closely with mask designers on custom design implementation, DFM and yield enhancement features
Deliver high quality design collateral
Collaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing, and power closure of the custom design
Interact with technology team, participate in developing design and test plans
Collaborate with CAD teams and drive design flow enhancements

Education and Experience