Apple
CPU Performance Architect - Platform Architecture
Apple, Santa Clara, California, us, 95053
CPU Performance Architect - Platform Architecture
Santa Clara, California, United States
Hardware
The CPU Platform Architecture team is responsible for pushing the boundaries of both single-threaded and multi-threaded CPU performance, to enhance the user experience of many Apple products. The team is composed of experts with deep experience in microarchitecture, ISA definition, performance modeling, power modeling, and workload analysis. We are seeking a highly motivated, innovative, and confident individual to join the CPU Platform Architecture team to help drive advanced exploration for next-generation iPhone, iPad, and Mac CPU designs.
Description
As a CPU Performance Architect with a focus on the memory subsystem, you will be part of a team that is defining and optimizing CPU and cache micro-architecture. Working collaboratively, you will seek out areas of the design for improvement by identifying performance bottlenecks and evaluate ideas to address them. You will engage with experienced CPU and SoC designers in micro-architecture and RTL to assess the feasibility of ideas through modeling, refine ideas and model correlation, and seed new ideas. The role requires the analysis of single-threaded and multi-threaded workloads across existing and new product categories to identify bottlenecks and opportunities for improvement. We collaborate as a larger CPU architecture and performance team to maintain and improve the simulation environment to enable data-driven decisions and always look for ways to boost the productivity of the entire team.
Minimum Qualifications
BS degree
Knowledge of CPU and SOC architecture and micro-architecture
Familiarity with performance simulation environments
Coding skills, including object-oriented programming with C/C++ and experience in scripting languages such as Perl or Python
Key Qualifications
Preferred Qualifications
Knowledge of memory latency tolerance techniques or other aspects of CPU memory subsystem (i.e. prefetching, caching policies)
15+ years of relevant industry experience
MS or PhD in Electrical or Computer Engineering or Computer Science
Understanding of common data structures and algorithms
Familiarity with SIMD, vector, or accelerator architectures
Familiarity with MP performance
Comfortable in an environment of uncertainty and able to navigate through ambiguities
Experience in a research-driven environment
Education & Experience
Additional Requirements
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $207,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.
Apple is an equal opportunity employer
that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
#J-18808-Ljbffr
that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
#J-18808-Ljbffr