ASIC Engineer

Want to be a part of a fast-paced team responsible for delivering high-speed ASICs for large, complex systems? Our team at Silicon Systems Technology Group (SST) is seeking ASIC Verification Engineers to verify the next generation of ASICs for new core routers, switches, and firewalls. We are looking to hire sharp individuals with excellent communication, problem-solving, and leadership skills.

Opportunity Snapshot:

At Juniper, you will have a significant opportunity to interact with system design teams across geographies. We are a team built on a foundation of open communications, empowerment, innovation, teamwork, and customer success with a "pay for performance" culture. Thus, you set your own limits for learning, achievements, and rewards.

Responsibilities:

1. You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.
2. Architect and develop block-level verification environments for sub-systems and full-chip using System Verilog and UVM methodology. (30%)
3. Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/NC) to perform this activity. (25%)
4. Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage, and gate-level simulation. (30%)
5. Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development. (10%)
6. Develop Perl, Python, and/or shell scripts to improve current verification infrastructure/methodology (5%)

Required Skills:

1. ASIC Verification using SystemVerilog
2. Experience in constrained-random verification is a strong plus
3. Experience with verification methodology like OVM/VMM/UVM
4. Perl/Tcl scripting is strongly preferred
5. Experience verifying networking protocols such as Ethernet is desirable
6. Strong problem-solving and ASIC debugging skills