Marvell Semiconductor, Inc.
System Validation SerDes Engineer, Sr. Staff
Marvell Semiconductor, Inc., Santa Clara, California, us, 95053
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a hardware and silicon validation senior staff engineer at Marvell, you'll be helping to deliver high bandwidth over long distances. This team performs analog validations on amplifiers that drive optical electronic devices and receivers. We also validate silicon photonics, do upper electronic measurements and support the coherent digital signal programming unit. This is a niche area at Marvell, working with cutting edge technologies used by many internal and external customers around the world.
What You Can Expect .Create, define and develop validation and test plans for Board/Chip level silicon validation/characterization on Marvell's internal IPs such as High-Speed SerDes, PLL, ADC, Power Regulator, Temperature sensor and others. Responsibility to implement the bench automation in Python to execute automatic data collection both using standard bench equipment and customized toolsets. Responsibility for the test setup and debug of failures. Requires understanding of system areas and interfaces with Architecture, Design, and Pre-silicon Validation High level overview and ability to understand end-to-end system scenarios. Detailed responsibilities include: Working with IP design team to define test specification arm to fully cover all items needed for IP validation and characterization. Responsible for device controlling SW (knowledge of Python, C++, Matlab, Excel VBA is a plus). Data analysis and silicon test report. Provide IP debugging support to SoC teams Provide IP usual training to Marvell's internal FAE. Work with IP design team on new chip features, definitions, and bring-up Develop technical collateral such as application notes, user guides, data sheet What We're Looking For .
General requirements: Bachelor's/Master's degree in Electrical engineering, Electronics and Communication engineering, Computer Science, Math, Physics, or related fields, 3-5 years of industry experience. Good fundamental knowledge in analog/digital circuit and data communication system. Working experience or knowledge in semiconductor chip lab testing and measurement, test script development, familiar with electronic test equipment. Working experience or knowledge in any of the following SerDes technologies is preferred. PCI Express, Ethernet, USB, SATA, SAS, CPRI, JESD, etc. Good communication skills in English and capable of independent work with less guidance. Thoughtful and perceptive analytical skills, logical thinking. Dedicated and committed to creative problem solving and getting things done. Prior experience in in HW validation, HW-SW integration, develop test plans for networking system features (Nice to have) Knowledge of high frequency lab instruments like DSO, SSA, VNA... (Nice to have) #LI-JS22 Expected Base Pay Range (USD) 137,510 - 206,000, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
TAOps@marvell.com. #LI-JS22 #J-18808-Ljbffr
What You Can Expect .Create, define and develop validation and test plans for Board/Chip level silicon validation/characterization on Marvell's internal IPs such as High-Speed SerDes, PLL, ADC, Power Regulator, Temperature sensor and others. Responsibility to implement the bench automation in Python to execute automatic data collection both using standard bench equipment and customized toolsets. Responsibility for the test setup and debug of failures. Requires understanding of system areas and interfaces with Architecture, Design, and Pre-silicon Validation High level overview and ability to understand end-to-end system scenarios. Detailed responsibilities include: Working with IP design team to define test specification arm to fully cover all items needed for IP validation and characterization. Responsible for device controlling SW (knowledge of Python, C++, Matlab, Excel VBA is a plus). Data analysis and silicon test report. Provide IP debugging support to SoC teams Provide IP usual training to Marvell's internal FAE. Work with IP design team on new chip features, definitions, and bring-up Develop technical collateral such as application notes, user guides, data sheet What We're Looking For .
General requirements: Bachelor's/Master's degree in Electrical engineering, Electronics and Communication engineering, Computer Science, Math, Physics, or related fields, 3-5 years of industry experience. Good fundamental knowledge in analog/digital circuit and data communication system. Working experience or knowledge in semiconductor chip lab testing and measurement, test script development, familiar with electronic test equipment. Working experience or knowledge in any of the following SerDes technologies is preferred. PCI Express, Ethernet, USB, SATA, SAS, CPRI, JESD, etc. Good communication skills in English and capable of independent work with less guidance. Thoughtful and perceptive analytical skills, logical thinking. Dedicated and committed to creative problem solving and getting things done. Prior experience in in HW validation, HW-SW integration, develop test plans for networking system features (Nice to have) Knowledge of high frequency lab instruments like DSO, SSA, VNA... (Nice to have) #LI-JS22 Expected Base Pay Range (USD) 137,510 - 206,000, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
TAOps@marvell.com. #LI-JS22 #J-18808-Ljbffr