Silicon Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

THE ROLE:

AMD's Adaptive and Embedded Computing Group (AECG) is seeking a Design Verification Engineer to contribute to high-speed Memory Controller and PHY/IO IP Verification. The individual will help design, develop and use digital simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of DDR, LPDDR, RLDRAM, QDR, HBM Memory Controllers, PHY/IO, and Network On-Chip (NOC) IPs, Subsystem, and SOC designs.

THE PERSON:

A Silicon Design Engineer will be a dynamic, quality-conscious, attention-oriented individual with industry or academic experience in successfully verifying products with high quality. Your experience and expertise in developing advanced SystemVerilog and UVM based testbench and Automation that can scale with Full-Chip will enable improved execution of AMD's devices and productivity. Candidate is expected to be a strong team player with good communication skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.

KEY RESPONSIBILITIES:

• Plan verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random and/or directed verification environments using System Verilog and UVM, or formally verify designs with SVA and industry leading formal tools.
• Identify and write all types of coverage measures for stimulus quality measurements.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

PREFERRED EXPERIENCE:

• Proficiency in System Verilog and UVM.
• Proficiency in C, Perl, Python and/or other scripting language.
• Prior experience with AXI Protocol, NoC architecture or DDR Protocol a plus.
• Candidate is expected to be a strong team player with good communication skills and one who is capable to work independently with an eye towards improving overall product quality.
• Understanding of state-of-the-art digital design and verification techniques, including simulation-based verification flow, assertion and metric-driven verification.
• Familiarity with verification management tools and understanding of database management particularly as it pertains to regression management.
• Prior use of simulation tools/debug environments such as Synopsys VCS, Synopsys VCS-XA, or Cadence IES is a strong plus.
• Basic understanding of formal property checking, gate level simulation, power verification using UPF, reset verification, and/or contention checking is a plus.

ACADEMIC QUALIFICATIONS:

• BS or MS in Electrical Engineering, Computer Science or related equivalent.

LOCATION: San Jose, CA

At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD's Employee Stock Purchase Plan. You'll also be eligible for competitive benefits described in more detail.