Digital ASIC Micro Architect Design Engineer

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in computer architecture concepts, including microarchitecture, multimedia architecture, and silicon design. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture. Experience architecting and designing low power SoC hardware IP in areas such as Camera ISP, video codecs, display, computer cores, and machine learning accelerators. Experience in ASIC development methodology and Verilog RTL development as per project demands. Experience collaborating cross-functionally with system and hardware architecture, IP design and verification, multi-media, and machine learning algorithm and software development teams. Familiarity with interconnect or fabric, security, and multi-level caching architectures. Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google ( https://careers.google.com/benefits/ ). Responsibilities: Develop System Verilog RTL to implement reasoning for ASIC or SoC products according to next-generation architecture specifications. Design digital verification of omit digital design blocks, and interact with architects to identify important verification scenarios. Perform detailed data analysis and trade-off evaluations to improve our hardware architecture solutions. Define and deliver the hardware IP architecture specifications that meet engaged power, performance, area, and image quality targets, which will require owning the goals through to tape-out and product launch. Collaborate with SoC and system architects on meeting dynamic power, performance, and area requirements at the SoC level for multimedia use cases and experiences. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity, or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also

https://careers.google.com/eeo/

and

https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf . If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form:

https://goo.gl/forms/aBt6Pu71i1kzpLHe2 .

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