Della Infotech, Inc.
Contract Hardware Engineer Mid. Job at Della Infotech, Inc. in Mountain View
Della Infotech, Inc., Mountain View, CA, United States, 94043
Duties: Location: Mountainview, California Exp: 10+ Years Note: Team is seeking a Design Verification candidate with Strong PCIe expertise along-with complex SoC debug is must. What You'll Be Doing: At-least 10+ years of experience in System Verilog HVL and C/C++. At least 10+ year of experience in SV/UVM. Porting/Testing in FPGA & Emulation (Zebu) Hardware realization Platform is good to have What We Are Looking For: Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Verification closure with team Make/Perl/Python Ensure customer satisfaction. Reporting to customers on daily or weekly progress effectively
Skills: Location: Mountainview, California Exp: 10+ Years Note: Team is seeking a Design Verification candidate with Strong PCIe expertise along-with complex SoC debug is must. What You'll Be Doing: At-least 10+ years of experience in System Verilog HVL and C/C++. At least 10+ year of experience in SV/UVM. Porting/Testing in FPGA & Emulation (Zebu) Hardware realization Platform is good to have What We Are Looking For: Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Verification closure with team Make/Perl/Python Ensure customer satisfaction. Reporting to customers on daily or weekly progress effectively
Education: Bachelor's / Masters / PhD
Required Skills: C/C++,SIMULATIONS,TEST PLAN,FPGA,VERILOG,
Additional Skills: DEBUG,FIELD PROGRAMMABLE GATE ARRAY,SOC,PERL,PCI EXPRESS,PYTHON,
Minimum Degree Required: Bachelor's Degree
Hours Per Day: 8.00
Hours Per Week: 40.00
Languages: English( Speak, Read, Write )
Department: Cost of goods sold : 1100
Job Category: IT
Skills: Location: Mountainview, California Exp: 10+ Years Note: Team is seeking a Design Verification candidate with Strong PCIe expertise along-with complex SoC debug is must. What You'll Be Doing: At-least 10+ years of experience in System Verilog HVL and C/C++. At least 10+ year of experience in SV/UVM. Porting/Testing in FPGA & Emulation (Zebu) Hardware realization Platform is good to have What We Are Looking For: Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Verification closure with team Make/Perl/Python Ensure customer satisfaction. Reporting to customers on daily or weekly progress effectively
Education: Bachelor's / Masters / PhD
Required Skills: C/C++,SIMULATIONS,TEST PLAN,FPGA,VERILOG,
Additional Skills: DEBUG,FIELD PROGRAMMABLE GATE ARRAY,SOC,PERL,PCI EXPRESS,PYTHON,
Minimum Degree Required: Bachelor's Degree
Hours Per Day: 8.00
Hours Per Week: 40.00
Languages: English( Speak, Read, Write )
Department: Cost of goods sold : 1100
Job Category: IT