Sivaltech
Senior design engineer
Sivaltech, San Diego, California, United States, 92189
Company Description
Sivaltech is an established ASIC/FPGA, Analog, Embedded Software design services company with offices in California, USA and Bangalore, India. The company serves as a preferred design services partner for Fortune 500 companies and startups in the semiconductor industry. With expertise in various domains including GPUs, CPUs, wireless, communications, and consumer electronics, Sivaltech is well-equipped to address complex design challenges for clients.
Job Title:
Senior Design Verification Engineer (Chip/IP Level) Location:
Bay Area, CA (On-site) Job Summary: We're seeking an experienced Design Verification Engineer to join our team in the Bay Area. The ideal candidate will have a strong background in chip-level verification, with expertise in standard interfaces like USB, I2C, and UART. Key Responsibilities: Develop and execute comprehensive verification plans for complex digital circuits and systems Design and implement testbenches using SystemVerilog/UVM Write and review test cases, simulation scripts, and coverage models Collaborate with design engineers to resolve design issues and improve verification efficiency Participate in design reviews and provide verification input Requirements: 8+ years of experience in design verification (chip-level or IP-level) Strong expertise in SystemVerilog/UVM, Verilog, and VHDL Experience with standard interfaces (USB, I2C, UART, etc.) Proficiency in simulation tools (VCS, QuestaSim, etc.) Excellent debugging and problem-solving skills Strong communication and teamwork skills Please share your updated resume at
Sridevi@sivaltech.com .
#J-18808-Ljbffr
Senior Design Verification Engineer (Chip/IP Level) Location:
Bay Area, CA (On-site) Job Summary: We're seeking an experienced Design Verification Engineer to join our team in the Bay Area. The ideal candidate will have a strong background in chip-level verification, with expertise in standard interfaces like USB, I2C, and UART. Key Responsibilities: Develop and execute comprehensive verification plans for complex digital circuits and systems Design and implement testbenches using SystemVerilog/UVM Write and review test cases, simulation scripts, and coverage models Collaborate with design engineers to resolve design issues and improve verification efficiency Participate in design reviews and provide verification input Requirements: 8+ years of experience in design verification (chip-level or IP-level) Strong expertise in SystemVerilog/UVM, Verilog, and VHDL Experience with standard interfaces (USB, I2C, UART, etc.) Proficiency in simulation tools (VCS, QuestaSim, etc.) Excellent debugging and problem-solving skills Strong communication and teamwork skills Please share your updated resume at
Sridevi@sivaltech.com .
#J-18808-Ljbffr