Silicon Senior Design Verification Engineer, TPU, Google Cloud

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 5 years of experience with verification methodology such as UVM/OVM/VMM. 3 years of experience in the verification of IP designs such as CPU, Peripherals, PMU, etc. Experience with SystemVerilog, SVA and functional coverage. Preferred qualifications: Master's degree in Electrical Engineering or a related field. 10 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs. Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Experience creating and using verification components and environments in standard verification methodology. Experience with ASIC standard interfaces and memory system architecture. Experience in verification of AI/ML Accelerators. About the job: In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will use your design and verification expertise to verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Additionally, you will be responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage. Responsibilities: Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools. Develop cross-language tools and scalable verification methodologies. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.

#J-18808-Ljbffr