ASIC Engineer

The application window is expected to close on 12/30/2024 This is an onsite role and will require working out of the Milpitas/San Jose office location. Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With Come join us and take part in shaping Cisco's revolutionary solutions for data centers by designing some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world What You'll Do The Core Hardware Business Unit is looking for a motivated Senior Verification engineer/lead to engage in new development of our UCS family. You will have an ASIC design and verification background with hands-on experience in RTL verification and in-depth knowledge of SoC development cycle and the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume semiconductor markets. Architect block, cluster and top level DV environment infrastructure Create DV infrastructure from scratch for block, cluster and top level environments Maintaining existing DV environments and enhancing them Ensuring complete verification coverage through implementation and review of code and functional coverage Working closely with designers Supporting tests done with emulation Work closely with software teams and debug issues found during firmware development Be responsible for ASIC bring up Minimum Qualifications 8+ years ASIC design verification

experience

with

Bachelor's or Master's degree in equivalent experience. Prior experience with ASIC verification using UVM/System Verilog. Prior

experience

verifying complex blocks, clusters and top level for SoC Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes. Prior

experience

with Perl and/or Python scripting Preferred Qualifications Domain experience on one or more protocols - PCIe, Ethernet, RDMA, TCP Prior experience with Forwarding logic/Parsers/P4 Prior experience with Veloce/Palladium/Zebu/HAPS Prior

experience

with formal verification (iev/vc formal)

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