ASIC Design Verification Engineer (all levels)

Client Overview
Our client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, we are targeting best in class latency with order of magnitude improvements for years to come.

Low Latency has become the key enabler for their industry and other real-time applications, and the current industry state-of-the-art is just not up to the task. Client has been developing its Neural Net Engines accelerators, optimizing it for Latency and achieving the best LPPA (Latency, Performance, Power, Area) in the field. We are now building the corresponding SoC to deliver unrivaled products to mission-critical and real-time applications.

This is a fast-paced, intellectually challenging position, and you will work with a talented team driven by innovation and excellence. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve our products' performance, quality, and cost.

We’re changing the meaning of low latency and we want individuals ready to rise up to the challenge and take the industry by storm.

Job Responsibilities

1. Architect and build an SoC-level and unit-level UVM verification environment.
2. Collaborate with Architecture and Design teams to verify the SoC features according to the chip use scenario.
3. Construct the chip level test plans, develop either directed or constrained random test vectors for closing the target coverage.
4. Participate in evaluating and selecting third-party VIPs and integrate them into the test bench.
5. Debug test failures by collaborating with stakeholders to identify the root cause of the issues.
6. Develop and maintain the daily and weekly regressions.

Required Skills

1. A minimum of 10+ years (Principal) / 7+ years (Senior Staff) / 5+ years (Staff) of design verification experience with 1+ years of leadership role (for Lead position).
2. Must possess prior experience in developing a complete chip-level UVM test bench from scratch (for Principal/Lead role).
3. Expert in coverage driven System Verilog UVM with DPI-C, including UVM runtime phases (for Lead/Principal role).
4. Proficient in programming in C/C++, Python, and/or scripting languages.
5. Prior experience in ASIC design verification.
6. In-depth knowledge in bus fabrics; NoC, AMBA, etc., in multi-CPU environments.

Nice to Have

1. Prior experience in verifying instruction driven designs like CPUs and GPGPUs.
2. Understanding of chip security, cold/warm boot sequences.
3. Experience using SERDES based high-speed interfaces, i.e., MIPI, PCIe, and USB.
4. FPGA prototyping experience.
5. Knowledge in ISO-26262 ASIL compliance.

Education

BSEE/BSCE required
Master in Science preferred.

Featured Benefits

• Medical insurance
• Vision insurance
• Dental insurance
• 401(k)