Physical Design Engineer

ASIC Physical Design Engineer Full Time Sunnyvale, California or Austin, Texas - Onsite Note: No hybrid or remote Job Description & Skill Requirement The role requires individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip (SoC) and IP for data center applications. Block level floorplanning and physical design activities for one or more blocks. Block level physical design includes floorplan, power plan, placement, CTS, timing analysis, and route optimization. Signoff timing and physical verification closure. As part of the block level implementation, you will need to ensure the floorplan is optimal, congestion issues are resolved, and timing is under control at every stage from synthesis, placement, CTS, and route stages. Signoff tasks include Timing closure with crosstalk and OCV under Multi-Mode Multi-corner conditions, Noise signoff, Physical verification including LVS, DRC, Antenna, and IR closure. Flow development/automation Qualification Minimum Qualifications Hands-on tape-out experience performing timing and physical verification closure on 5nm FinFET TSMC process or similar/lower technology nodes Hands-on experience with block level physical design (Floorplanning to GDSII) Experience with SoC level integration (multiple blocks, SoC floorplan, clocking, and timing analysis) preferred Expertise in Cadence (Innovus) P&R, Synopsys PrimeTime/StarRC/ICV, Ansys Redhawk, and Mentor Graphics Caliber EDA tools Proficiency in scripting languages, such as Makefiles, Tcl, Unix Shell, Python Hands-on experience in writing scripts to improve or develop flow from scratch Solid engineering understanding of the underlying concepts of IC design, implementation flows, and methodologies for deep submicron design 10 years industry experience, BS EE Preferred Qualifications Experience in full chip floor planning, partitioning, budgeting, and power grid planning. Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge. Experience in planning, implementing, and analyzing high-speed clock distribution networks. Experience with alternate strategies for clock distribution, including standard trees, mesh, H-Tree, and clock power reduction techniques. Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions. Knowledge of Circuit design, device physics, and deep sub-micron technology. Experience in the physical design of data-path intensive designs. Experience in the 3D-IC technology, methodology, and advanced packaging. Experience in validating Power Distribution Network (PDN), IR/EM, Thermals for 3D-IC.