Apple Inc.
Technology PPA Engineer
Apple Inc., Cupertino, California, United States, 95014
As part of the Silicon Technology team, you’ll help design our next-generation, high-performance, power-efficient SoCs. You will explore various technology what-if questions to find the overall optimal for Apple’s products. This will involve exploring various device knobs, stdcells, and wiring configurations to sweet spot the technology for Apple's needs. You will collaborate with design teams to define the best technology and flows to maximize the impact on our designs. You will work on world-class CPU, GPU, and SOC designs by helping define and explore new std cell architectures and new flows that have a PPA (Power, Performance, Area) impact on Apple products! We are looking for passionate engineers to join our team. In this role, you will be impacting a wide range of chips used across Apple’s world-class products!
Description
Participating and leading cross-functional teams to solve key technology definition and design challenges. Explore various technology questions and knobs to maximize PPA. Explore and help define std cell architectures and flows to maximize the PPA for CPUs, GPUs, and SOC designs. Collaborate with CAD teams to help create flows for future technology. Collaborating with other disciplines such as physical design verification, RC extraction, IR, and static timing analysis (STA). Minimum Qualifications
Bachelor's degree and a minimum of 3 years relevant industry experience. Preferred Qualifications
Electrical engineering fundamentals in digital circuits, timing/power concepts, and logic design. Basic scripting skills to interface with tools and mining data. Experience in using industry-standard synthesis, PnR, and STA tools. Understanding of technology or experience in advanced technology would be a plus. Expert in CAD flow or PD methodology development. Experience with advanced technology node and std cell architecture/definition. Proficiency with Tcl, Python, or Perl scripting languages. Hands-on knowledge of industry-standard PNR tools. Expertise in analysis aspects of Physical Design - extraction, timing, noise, physical verification, EMIR.
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Participating and leading cross-functional teams to solve key technology definition and design challenges. Explore various technology questions and knobs to maximize PPA. Explore and help define std cell architectures and flows to maximize the PPA for CPUs, GPUs, and SOC designs. Collaborate with CAD teams to help create flows for future technology. Collaborating with other disciplines such as physical design verification, RC extraction, IR, and static timing analysis (STA). Minimum Qualifications
Bachelor's degree and a minimum of 3 years relevant industry experience. Preferred Qualifications
Electrical engineering fundamentals in digital circuits, timing/power concepts, and logic design. Basic scripting skills to interface with tools and mining data. Experience in using industry-standard synthesis, PnR, and STA tools. Understanding of technology or experience in advanced technology would be a plus. Expert in CAD flow or PD methodology development. Experience with advanced technology node and std cell architecture/definition. Proficiency with Tcl, Python, or Perl scripting languages. Hands-on knowledge of industry-standard PNR tools. Expertise in analysis aspects of Physical Design - extraction, timing, noise, physical verification, EMIR.
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