Apple Inc.
DDR Design Engineer
Apple Inc., San Diego, California, United States, 92189
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented DRR Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. You will join the DDR PHY design team. We provide best-in-class PHY designs for high-performance, low power applications. As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
Description
In this role, you will be responsible for the following: Performing concept studies and providing direction in terms of performance, gate count, and power for various digital designs. Writing detailed design specifications and test plans in close collaboration with architecture, circuit designers, and verification engineers. Providing high-quality RTL description, including assertions, for the design. Using formal tools and static checkers to guarantee RTL quality. Supporting design verification to ensure bug-free first silicon. Driving functional and code coverage as well as timing closure for your designs. Supporting silicon bring-up, performance, and power characterization. Minimum Qualifications
BS degree in a technical discipline with a minimum of 10 years of relevant experience. Preferred Qualifications
RTL design using Verilog or SystemVerilog, assertion writing. Design of state machines, data paths, arbitration, and clock domain crossing logic. Logic synthesis, timing constraints. Exposure to Design For Test, understanding of scan concept, and writing DFT friendly RTL. Unified Power Format for simulation, synthesis, and electrical rule checking equivalence checking. Prior experience in DDR PHY design and mixed-signal environment is a plus. Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
#J-18808-Ljbffr
In this role, you will be responsible for the following: Performing concept studies and providing direction in terms of performance, gate count, and power for various digital designs. Writing detailed design specifications and test plans in close collaboration with architecture, circuit designers, and verification engineers. Providing high-quality RTL description, including assertions, for the design. Using formal tools and static checkers to guarantee RTL quality. Supporting design verification to ensure bug-free first silicon. Driving functional and code coverage as well as timing closure for your designs. Supporting silicon bring-up, performance, and power characterization. Minimum Qualifications
BS degree in a technical discipline with a minimum of 10 years of relevant experience. Preferred Qualifications
RTL design using Verilog or SystemVerilog, assertion writing. Design of state machines, data paths, arbitration, and clock domain crossing logic. Logic synthesis, timing constraints. Exposure to Design For Test, understanding of scan concept, and writing DFT friendly RTL. Unified Power Format for simulation, synthesis, and electrical rule checking equivalence checking. Prior experience in DDR PHY design and mixed-signal environment is a plus. Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
#J-18808-Ljbffr