Rival
Senior Memory Design Engineer
Rival, Santa Clara, California, us, 95053
Rivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, and compiled memories to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly. The qualified candidate will be responsible for designing and delivering custom circuits from scratch. Candidates must have 8-10 years of experience in transistor level circuit design, circuit simulation, equivalence checking, PPA trade off analysis, low power design techniques, timing, noise and power characterization.
Key Qualifications
The ideal candidate will have 10 years of custom circuit design experience from RTL-GDS for CPU and SoC applicationsPrior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cellsExperience designing transistor-level custom circuits in advanced FinFET technology nodesMust have a solid experience with the custom circuit tool flows for delivering design collaterals.A solid understanding of device physics, process technology and circuit design techniques for high performance, low powerExperience with advanced process design rules and supervising mask designKnowledge developing automation for compilers and standard cellsPost-Silicon test and debug experienceAbility to work well in a team and be productive under aggressive schedules.Excellent problem solving, written and verbal communicationResponsibilities
Drive design and development of SRAM, register file, custom cells to enable high performance and low power designsWork with microarchitecture team to gather specifications and drive optimal implementationConduct early sizing estimates and PPA analysis. Design entry and simulations for optimal design sizing.Design equivalence checking using the latest industry standard LEC toolsWork closely with mask designers on custom design implementation, DFM and yield enhancement featuresDeliver high quality design collateralCollaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom designInteract with technology team, participate in developing design and test plansCollaborate with CAD teams and drive design flow enhancementsEducation and Experience
Master’s Degree or Bachelor’s Degree with 8-10 years of experience
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Key Qualifications
The ideal candidate will have 10 years of custom circuit design experience from RTL-GDS for CPU and SoC applicationsPrior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cellsExperience designing transistor-level custom circuits in advanced FinFET technology nodesMust have a solid experience with the custom circuit tool flows for delivering design collaterals.A solid understanding of device physics, process technology and circuit design techniques for high performance, low powerExperience with advanced process design rules and supervising mask designKnowledge developing automation for compilers and standard cellsPost-Silicon test and debug experienceAbility to work well in a team and be productive under aggressive schedules.Excellent problem solving, written and verbal communicationResponsibilities
Drive design and development of SRAM, register file, custom cells to enable high performance and low power designsWork with microarchitecture team to gather specifications and drive optimal implementationConduct early sizing estimates and PPA analysis. Design entry and simulations for optimal design sizing.Design equivalence checking using the latest industry standard LEC toolsWork closely with mask designers on custom design implementation, DFM and yield enhancement featuresDeliver high quality design collateralCollaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom designInteract with technology team, participate in developing design and test plansCollaborate with CAD teams and drive design flow enhancementsEducation and Experience
Master’s Degree or Bachelor’s Degree with 8-10 years of experience
#J-18808-Ljbffr