SoC/ASIC Design Engineer

zeroRISC is committed to enabling trust in critical systems via transparently implemented security foundations. We embrace the use of open source technologies as a practical starting point for accessible, trustworthy, commercial engineering of secure systems. We contribute extensively to the OpenTitan open source silicon root of trust project and consider visibility a necessary precondition to building trust and reducing risk.As a zeroRISC SoC/ASIC Design Engineer, you will be responsible for designing and delivering security-centric chips. You will develop secure silicon, including root of trust technology, utilizing and contributing to open-source implementations. You will design ASICs at top or block levels including foundational system security, stability and safety. You will collaborate to help drive products through the full ASIC development lifecycle, from architecture through tapeout and silicon validation.Minimum Qualifications

Bachelor’s degree in Electrical Engineering or Computer Science, or a related technical field or equivalent experience4 years of experience with architecture and design of SystemVerilog-based chips and IP blocksExperience with design flows including lint, synthesis and timing closure (e.g. SDF)Experience with multipower and multiclock domain designsPreferred Qualifications

Master’s or PhD in Electrical Engineering or Computer Science, or a related technical field or equivalent experienceKnowledge of security ASICs or accelerators (e.g. cryptography accelerators or GPUs)Knowledge of computer architecture and memory subsystem architecturesExperience designing standard components such as ALUs and caches and standard interfaces such as USB and I2CExperience with IP block integrationExperience with UPF and power analysis and estimationExperience with CDC and RDCExperience with DFD, DFT, and design for verificationExperience with FPGA and emulation platformsExperience with assertion codingExperience with scripting languages such as PythonResponsibilities

Execute full design lifecycle from architecture definition through design sign off and post silicon validationDesign ASICs/SOCs at the chip/top or block levelsAchieve product goals by trading off functionality, performance, power, area and scheduleWrite thorough design specificationsCode high quality SystemVerilog based RTL designs including engineering best practicesParticipate with verification team on test plan definition, debug, and coverage closureCollaborate with architecture, verification, physical design, test, software, system, emulation, and silicon validation teams to ensure high quality full system design functionality and implementation through the whole development processCollaborate with engineering program managers to effectively and efficiently deliver high quality, on schedule project execution

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