Minster Bank
Senior ASIC Design Engineer USA Tech Recruitment
Minster Bank, San Jose, California, United States, 95199
Senior ASIC Design Engineer
San Jose – California
This role focuses on steering the microarchitecture and design of a groundbreaking convolutional neural network accelerator ASIC. It’s pivotal for a flagship autonomous driving perception module, ensuring top-tier computational performance with minimal power consumption.
Responsibilities:
– Drafting micro-architecture specifications and contributing to reviews.
– Architecting and implementing complex RTL designs.
– Integrating critical IPs, including CPUs, into the subsystem.
– Collaborating on issue resolution and power optimization.
– Analyzing code coverage and assisting in post-silicon validation.
Requirements:
– 5+ years’ experience in RTL logic design for multi-million gate ASICs.
– Expertise in integrating CPU IP into SoCs.
– Proficiency in ARM/RISC-V/MIPS Architectures and memory hierarchy.
– Familiarity with AMBA/APB/AXI Protocol and processor peripheral interfaces.
– Track record in low-power design and UPF flow.
– Interest in AI architectures and thriving in a dynamic startup setting.
– Bachelor’s degree (Master’s preferred) in Electrical/Computer Engineering.
If this sounds interesting and you’d like to learn more, click the link below to apply or email me with a copy of your CV on ik@eu-recruit.com
By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)
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San Jose – California
This role focuses on steering the microarchitecture and design of a groundbreaking convolutional neural network accelerator ASIC. It’s pivotal for a flagship autonomous driving perception module, ensuring top-tier computational performance with minimal power consumption.
Responsibilities:
– Drafting micro-architecture specifications and contributing to reviews.
– Architecting and implementing complex RTL designs.
– Integrating critical IPs, including CPUs, into the subsystem.
– Collaborating on issue resolution and power optimization.
– Analyzing code coverage and assisting in post-silicon validation.
Requirements:
– 5+ years’ experience in RTL logic design for multi-million gate ASICs.
– Expertise in integrating CPU IP into SoCs.
– Proficiency in ARM/RISC-V/MIPS Architectures and memory hierarchy.
– Familiarity with AMBA/APB/AXI Protocol and processor peripheral interfaces.
– Track record in low-power design and UPF flow.
– Interest in AI architectures and thriving in a dynamic startup setting.
– Bachelor’s degree (Master’s preferred) in Electrical/Computer Engineering.
If this sounds interesting and you’d like to learn more, click the link below to apply or email me with a copy of your CV on ik@eu-recruit.com
By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)
#J-18808-Ljbffr