Senior Physical Design Engineer

Physical design for high-performance designs going into industry leading AI/ML architecture. The person coming into this role will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip. The work is done alongside a group of highly experienced engineers across various domains of the AI chip.Responsibilities:

Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cyclePhysical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimizationDiscussions with 3rd party IP providers, foundry partners and design servicesEnd to end tasks from flow development to sign-offDeploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power resultsExperience & Qualifications

BS/MS/PhD in EE/ECE/CE/CSHands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and toolsStrong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flowsExperience with back-end design tools such as Primetime, Innovus, RedHawk, etc.Knowledge of low-power design flows such as power gating, multi-Vt and voltage scalingStrong programming skills in Tcl/Perl/Shell/PythonExcellent understanding of logic design fundamentals and gate/transistor level implementationExposure to DFT is an assetPrior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutionsStrong problem solving and debug skills across various levels of design hierarchies

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