Tenstorrent Inc
Staff Engineer, CPU Formal Verification
Tenstorrent Inc, Austin, Texas, us, 78716
CPU Formal Verification engineer will be responsible for applying various formal verification techniques to source bugs in specifications and RTL implementation for a high performance data center class CPU.
This role ishybrid, based out of Austin, TX or Santa Clara, CA.
Responsibilities:
Drive formal verification for block across CPU design by interacting with the team and scoping out the complexity of the problem at hand
Develop detailed verification plans to highlight the checks and constraints
Develop assertions, cover properties and connectivity checks as a part of formal verification flows and debug any failures in regressions
Create formal verification flows and deploy techniques that leverage on both industry standard and open-source tools. Drive automation of formal testbenches and ensure they are a part of regressions
Deploy scripts and automation to support formal, review setups and proofs with Microarchitecture and DV engineers
Experience & Qualifications:
BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
Prior experience with formal verification methods and techniques
Strong knowledge of computer architecture with some experience on CPU, GPU, Cache designs
Hands-on experience with formal verification tools such as Jasper, VC-Formal, Yosys, IFV, Questa, etc.
Proficiency in programing/scripting languages
Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator), experience capturing design specification in a temporal assertion language such as SVA
Strong problem solving and debug skills for complex logic and digital designs
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.
Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject toU.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee informationand/or documentation will be required and considered as Tenstorrent moves through the employment process.
If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.
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This role ishybrid, based out of Austin, TX or Santa Clara, CA.
Responsibilities:
Drive formal verification for block across CPU design by interacting with the team and scoping out the complexity of the problem at hand
Develop detailed verification plans to highlight the checks and constraints
Develop assertions, cover properties and connectivity checks as a part of formal verification flows and debug any failures in regressions
Create formal verification flows and deploy techniques that leverage on both industry standard and open-source tools. Drive automation of formal testbenches and ensure they are a part of regressions
Deploy scripts and automation to support formal, review setups and proofs with Microarchitecture and DV engineers
Experience & Qualifications:
BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
Prior experience with formal verification methods and techniques
Strong knowledge of computer architecture with some experience on CPU, GPU, Cache designs
Hands-on experience with formal verification tools such as Jasper, VC-Formal, Yosys, IFV, Questa, etc.
Proficiency in programing/scripting languages
Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator), experience capturing design specification in a temporal assertion language such as SVA
Strong problem solving and debug skills for complex logic and digital designs
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.
Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject toU.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee informationand/or documentation will be required and considered as Tenstorrent moves through the employment process.
If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.
#J-18808-Ljbffr