Western Digital Capital
Technologist - Analog/Mixed-Signal IC Design Engineer
Western Digital Capital, San Jose, California, United States, 95199
Technologist - Analog/Mixed-Signal IC Design Engineer
Full-time Job Type (exemption status): Exempt position Salary Range: 154,360.00-218,700.00 Business Function: ASIC Development Engineering At Western Digital, our vision is to power global innovation and push the boundaries of technology. Circuit designer will be responsible for the design of high performance analog circuit blocks. Responsibilities include block level and transistor level circuit design and simulation, layout supervision and verification, preparation of test plan for the test group, product characterization, reliability and yield assessment and modeling, simulation to bench and bench to test correlation, bench evaluation both at silicon level and at applications level, and documentation. Job responsibilities involve the ability to communicate at all levels and with cross functional groups, and requires good verbal and written communications skills. Engineer must have a demonstrated track record of circuit innovation, be a team player, be adaptable, and accept criticism. REQUIRED FOR CONSIDERATION MSEE with 12+ years of experience in circuit design and development Must have
experience in at least one preferably multiple area of full CMOS circuit design and development in:
Baseband amplifiers, low noise amplifiers, wide bandwidth amplifiers High performance high resolution ADC and DAC High speed drivers and receivers, CDR, equalization Power management, LDO regulators and high stability references
Must have
experience in 40nm and below full CMOS technology Must have
a demonstrable track record of successful design releases and mass production Must have
thorough knowledge of industry standard EDA tools (Cadence, Mentor etc.) Must have
experience with layout of high performance analog blocks such as analog to digital converters, references, digital to analog converters etc. Must have
experience with floor planning, block level routing and top level chip routing Must have
knowledge of high performance analog layout techniques, EM-IR and SOA considerations Must have
experience working with distributed design teams a plus Must possess strong written and verbal communication skills
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Full-time Job Type (exemption status): Exempt position Salary Range: 154,360.00-218,700.00 Business Function: ASIC Development Engineering At Western Digital, our vision is to power global innovation and push the boundaries of technology. Circuit designer will be responsible for the design of high performance analog circuit blocks. Responsibilities include block level and transistor level circuit design and simulation, layout supervision and verification, preparation of test plan for the test group, product characterization, reliability and yield assessment and modeling, simulation to bench and bench to test correlation, bench evaluation both at silicon level and at applications level, and documentation. Job responsibilities involve the ability to communicate at all levels and with cross functional groups, and requires good verbal and written communications skills. Engineer must have a demonstrated track record of circuit innovation, be a team player, be adaptable, and accept criticism. REQUIRED FOR CONSIDERATION MSEE with 12+ years of experience in circuit design and development Must have
experience in at least one preferably multiple area of full CMOS circuit design and development in:
Baseband amplifiers, low noise amplifiers, wide bandwidth amplifiers High performance high resolution ADC and DAC High speed drivers and receivers, CDR, equalization Power management, LDO regulators and high stability references
Must have
experience in 40nm and below full CMOS technology Must have
a demonstrable track record of successful design releases and mass production Must have
thorough knowledge of industry standard EDA tools (Cadence, Mentor etc.) Must have
experience with layout of high performance analog blocks such as analog to digital converters, references, digital to analog converters etc. Must have
experience with floor planning, block level routing and top level chip routing Must have
knowledge of high performance analog layout techniques, EM-IR and SOA considerations Must have
experience working with distributed design teams a plus Must possess strong written and verbal communication skills
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