Esperanto.ai
SR PERIPHERAL SUBSYSTEM DESIGN ENGINEER
Esperanto.ai, Mountain View, California, us, 94039
We are looking for a candidate to join our next generation Systems on a Chip (SOC) RTL design team. The candidate will be a part of the I/O design team responsible for specifying, implementing and integrating Verilog RTL IPs into our custom high performance, energy efficient AI processor.Responsibilities
Integrate 3 rd
party vendor’s Verilog IP into standard bus protocolsWrite microarchitecture specificationsWork with design verification team to draft test plans, debug test failures and to ensure functional correctnessSynthesize RTL to logic gates using standard CAD tools and build timing and area constraintsInteract closely with physical design team to guarantee proper backend implementationSupport Silicon bringup and diagnosticsEvaluate potential new vendor’s I/O IP for use in next generation designQualifications
BS in EE or related technical field+5 years in ASIC/SOC design and Verilog RTL coding experienceCompleted ASIC/SOC design projects with successful tapeoutsExperience in industrial standard ASIC/SOC CAD tools for simulation, synthesis, debug, timing analysis and power estimationExperience with PCIe Controller and PHY IPsExperience with AXI interfaceExcellent verbal and written communication skillsAdditional Success Factors
Knowledge of I/O protocols such as SMBus, PCI Express, UARTPrevious projects using Synopsys CAD toolsExperience in ASIC/SOC designs with multiple power and clock domains, and integrating UPF into design flowExperience in low-power SOC designKnowledge of scripting and automation in Linux environmentStrong planning, organizational, problem solving and analytical skill set; supported by critical thinking and attention to details, and be able to negotiate, assert and communicate effectively.A team player in a chip design startup environment who is able to interact with sites in different geographical locations and time zones.Benefits
Base salary range is $100,000 - $300,000The actual salary of a successful applicant may vary from the posted range based on a candidate’s experience, training, education, location and/or other legitimate business reasons.You will also be eligible for stock options and benefits.
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Integrate 3 rd
party vendor’s Verilog IP into standard bus protocolsWrite microarchitecture specificationsWork with design verification team to draft test plans, debug test failures and to ensure functional correctnessSynthesize RTL to logic gates using standard CAD tools and build timing and area constraintsInteract closely with physical design team to guarantee proper backend implementationSupport Silicon bringup and diagnosticsEvaluate potential new vendor’s I/O IP for use in next generation designQualifications
BS in EE or related technical field+5 years in ASIC/SOC design and Verilog RTL coding experienceCompleted ASIC/SOC design projects with successful tapeoutsExperience in industrial standard ASIC/SOC CAD tools for simulation, synthesis, debug, timing analysis and power estimationExperience with PCIe Controller and PHY IPsExperience with AXI interfaceExcellent verbal and written communication skillsAdditional Success Factors
Knowledge of I/O protocols such as SMBus, PCI Express, UARTPrevious projects using Synopsys CAD toolsExperience in ASIC/SOC designs with multiple power and clock domains, and integrating UPF into design flowExperience in low-power SOC designKnowledge of scripting and automation in Linux environmentStrong planning, organizational, problem solving and analytical skill set; supported by critical thinking and attention to details, and be able to negotiate, assert and communicate effectively.A team player in a chip design startup environment who is able to interact with sites in different geographical locations and time zones.Benefits
Base salary range is $100,000 - $300,000The actual salary of a successful applicant may vary from the posted range based on a candidate’s experience, training, education, location and/or other legitimate business reasons.You will also be eligible for stock options and benefits.
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