P. Chappel Associates, Inc.
Physical Design Engineer
P. Chappel Associates, Inc., Santa Clara, California, us, 95053
Physical Design Engineer – Santa Clara, CaliforniaPermanent position – $120K-$160K base salaryUnique opportunity to join an established international company in their North America expansion. Working from the NA headquarters, you will have the ability to be an impact player working with some other exceptionally talented people. The Physical Design Engineer will be responsible for the entire product design lifecycle.Duties include:
Actively participate and contribute in technical and schedule discussions with customers, colleagues, and managers.Chip Level Floor planningPlacementClock Tree SynthesisOptimizationRoutingParasitic ExtractionStatic Timing AnalysisPower consumption AnalysisIR drop / Emig / DvD analysisPhysical Verification and Sign OffMultiple P&R blocks to benchmark QORWork closely and collaborate with frontend and integration teams to ensure successful tape outsMeet deliverables within the allotted deadlinesQualifications include:
BSEE. MSEE preferred.5-10 years of experience in cutting edge submicron physical design flows.Experience in Physical Design Implementation which includes Floorplan, Chip Partitioning, Power mesh, Clock Tree, Physical optimization, Place and Route, STA, Timing closure, Power analysis and Physical Verification.Experience in both Flat and Hierarchical layout.Experience with tape out designs in 28nm and 16nm/12nm technology node.Hands on experience ICC2 and Innovus.Calibre or ICV physical verification tool experience for DRC/LVS/ERC/ANT.Good understanding of ASIC Front-End Design.Good interpersonal and communication skills.Japanese language skills a plus.
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Actively participate and contribute in technical and schedule discussions with customers, colleagues, and managers.Chip Level Floor planningPlacementClock Tree SynthesisOptimizationRoutingParasitic ExtractionStatic Timing AnalysisPower consumption AnalysisIR drop / Emig / DvD analysisPhysical Verification and Sign OffMultiple P&R blocks to benchmark QORWork closely and collaborate with frontend and integration teams to ensure successful tape outsMeet deliverables within the allotted deadlinesQualifications include:
BSEE. MSEE preferred.5-10 years of experience in cutting edge submicron physical design flows.Experience in Physical Design Implementation which includes Floorplan, Chip Partitioning, Power mesh, Clock Tree, Physical optimization, Place and Route, STA, Timing closure, Power analysis and Physical Verification.Experience in both Flat and Hierarchical layout.Experience with tape out designs in 28nm and 16nm/12nm technology node.Hands on experience ICC2 and Innovus.Calibre or ICV physical verification tool experience for DRC/LVS/ERC/ANT.Good understanding of ASIC Front-End Design.Good interpersonal and communication skills.Japanese language skills a plus.
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