Renesas Electronics
Sr Device Process Engineer
Renesas Electronics, San Jose, California, United States, 95199
Job Description
An experienced researcher in the area of compound semiconductor responsible for development of new and innovative epitaxy design in GaN on Silicon process technology to achieve best in class linearity and power added efficiency HEMT devices for PA design. The candidate will be responsible for collaboration with foundry and academic partners, devising new process flow using TCAD tools, design and layout of appropriate test structures, and testchip tape out to candidate fabs. The candidate will also be responsible for characterization and measurement of the testchip to verify the targeted performance improvement and publish report and present the result to the team. Upon achieving the performance target the candidate will be responsible for developing a compact model and implements it in PDK for design team to use for design of final product. The candidate will work closely with the design team to achieve the final product tape out.
Responsibilities:
Literature search with emphasis on the area of GaN devices on Silicon
Perform TCAD simulation using Sentaurus tool from Synopsis to design GaN epitaxy experiments to enhance HEMT performance and reliability
Test structure design and layout and tapeout testchip
Perform Device characterization using DC, CV, and RF characterization
Perform CW and pulsed IV, S-parameter, and Load-Pull (LP) measurement
Perform device level circuit simulation using Cadence and ADS tools
Compact model development using CMC standard model for GaN devices.
Qualifications:
MS or PHD in EE, Physics, or Material Science with research focus on GaN epitaxy, GaN HEMT, or GaAs pHEMT/HBT
Good understanding of high band gap GaN or GaAs device physics and fabrication process
Good understanding of device reliability issues in III-V devices
Good understanding of GaN or GaAs epitaxy growth process
TCAD simulation of high band gap GaN or GaAs devices
Experience with measurements techniques such as DC and pulsed IV, CV, CW and pulsed S-parameter as well as load-pull characterization
Good written/oral communication and project management skills
The expected annual pay range for this position is $96,500 - $145,000. This position is also eligible for bonus opportunities. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate.
Renesas Electronics is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law.
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An experienced researcher in the area of compound semiconductor responsible for development of new and innovative epitaxy design in GaN on Silicon process technology to achieve best in class linearity and power added efficiency HEMT devices for PA design. The candidate will be responsible for collaboration with foundry and academic partners, devising new process flow using TCAD tools, design and layout of appropriate test structures, and testchip tape out to candidate fabs. The candidate will also be responsible for characterization and measurement of the testchip to verify the targeted performance improvement and publish report and present the result to the team. Upon achieving the performance target the candidate will be responsible for developing a compact model and implements it in PDK for design team to use for design of final product. The candidate will work closely with the design team to achieve the final product tape out.
Responsibilities:
Literature search with emphasis on the area of GaN devices on Silicon
Perform TCAD simulation using Sentaurus tool from Synopsis to design GaN epitaxy experiments to enhance HEMT performance and reliability
Test structure design and layout and tapeout testchip
Perform Device characterization using DC, CV, and RF characterization
Perform CW and pulsed IV, S-parameter, and Load-Pull (LP) measurement
Perform device level circuit simulation using Cadence and ADS tools
Compact model development using CMC standard model for GaN devices.
Qualifications:
MS or PHD in EE, Physics, or Material Science with research focus on GaN epitaxy, GaN HEMT, or GaAs pHEMT/HBT
Good understanding of high band gap GaN or GaAs device physics and fabrication process
Good understanding of device reliability issues in III-V devices
Good understanding of GaN or GaAs epitaxy growth process
TCAD simulation of high band gap GaN or GaAs devices
Experience with measurements techniques such as DC and pulsed IV, CV, CW and pulsed S-parameter as well as load-pull characterization
Good written/oral communication and project management skills
The expected annual pay range for this position is $96,500 - $145,000. This position is also eligible for bonus opportunities. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate.
Renesas Electronics is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law.
#J-18808-Ljbffr