Tbwa Chiat/Day Inc
Senior Engineer, VLSI Design Bangalore, India
Tbwa Chiat/Day Inc, California, Missouri, United States, 65018
InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology.As
Senior Engineer, VLSI Design , you will be the key contributor of ORAN SoC product development in the design team and collaborate with FW & design team for product requirement definition, micro architecture study. You will participate in the implementation & verification of novel ORAN SoC functional blocks for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations. Beyond the technical contribution, you will also interface with functional leads in project coordination for schedule tracking on deliverables and dependencies. You will provide technical advice to young engineers to ensure the quality of work. This role is an excellent opportunity for engineers with 5+ years of industrial experience to grow their technical career as well as leadership to climb up corporate ladders and join the exciting cellular product market space.This position will be based in
Bangalore, India.Key ResponsibilitiesParticipate in SoC specifications reviews and contribute to micro-architecture definitions.Front end digital design and implementation – RTL coding, CDC, Lint, and synthesis.Develop design constraints and coordinate to debug both functional and DFT test issues.Supervise/mentor young engineers for task assignment and ensure productivity and quality.Project coordination and status update.Help to improve SoC design methodologies and verification quality.Support IP/Design Verification/Firmware/Software System/Production teams to provide the necessary support for timely closure of assigned blocks design and implementation issues.Job RequirementsMaster's and/or bachelor’s degree in engineering (or equivalent) in EC/ EE/ CS.5 or more years of experience in digital SoC development with proven experience from full chip development to tape-out sign-off.Experience in RTL design using Verilog/SystemVerilog/VHDL for CPU/control sub-systems (AXI/AHB/APB bus), digital signal processing blocks (FIR filter, FFT/IFFT, NCO).Experience of front-end tools (Verilog simulators, linters, clock-domain-crossing checkers).Experience in gate level simulation and LEC checking.Good understanding of back-end design flow on logic synthesis, constraints, timing analysis, DFT.Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques.Knowledge of languages such as C/C++, Perl, Tcl, and Python.Good verbal and written communication and presentation skills.Team player with the ability to collaborate with cross-functional teams to resolve issues effectively.RTL coding & simulation in Verilog/SystemVerilog/VHDL.Design simulation & checking with Cadence front end tools: Xcelium, SimVision, Jasper RTL Apps.Python, Perl scripting for verification automation and report generation.MS Office tools: Excel, PowerPoint, Word doc, Visio.
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Senior Engineer, VLSI Design , you will be the key contributor of ORAN SoC product development in the design team and collaborate with FW & design team for product requirement definition, micro architecture study. You will participate in the implementation & verification of novel ORAN SoC functional blocks for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations. Beyond the technical contribution, you will also interface with functional leads in project coordination for schedule tracking on deliverables and dependencies. You will provide technical advice to young engineers to ensure the quality of work. This role is an excellent opportunity for engineers with 5+ years of industrial experience to grow their technical career as well as leadership to climb up corporate ladders and join the exciting cellular product market space.This position will be based in
Bangalore, India.Key ResponsibilitiesParticipate in SoC specifications reviews and contribute to micro-architecture definitions.Front end digital design and implementation – RTL coding, CDC, Lint, and synthesis.Develop design constraints and coordinate to debug both functional and DFT test issues.Supervise/mentor young engineers for task assignment and ensure productivity and quality.Project coordination and status update.Help to improve SoC design methodologies and verification quality.Support IP/Design Verification/Firmware/Software System/Production teams to provide the necessary support for timely closure of assigned blocks design and implementation issues.Job RequirementsMaster's and/or bachelor’s degree in engineering (or equivalent) in EC/ EE/ CS.5 or more years of experience in digital SoC development with proven experience from full chip development to tape-out sign-off.Experience in RTL design using Verilog/SystemVerilog/VHDL for CPU/control sub-systems (AXI/AHB/APB bus), digital signal processing blocks (FIR filter, FFT/IFFT, NCO).Experience of front-end tools (Verilog simulators, linters, clock-domain-crossing checkers).Experience in gate level simulation and LEC checking.Good understanding of back-end design flow on logic synthesis, constraints, timing analysis, DFT.Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques.Knowledge of languages such as C/C++, Perl, Tcl, and Python.Good verbal and written communication and presentation skills.Team player with the ability to collaborate with cross-functional teams to resolve issues effectively.RTL coding & simulation in Verilog/SystemVerilog/VHDL.Design simulation & checking with Cadence front end tools: Xcelium, SimVision, Jasper RTL Apps.Python, Perl scripting for verification automation and report generation.MS Office tools: Excel, PowerPoint, Word doc, Visio.
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