Intel GmbH
CPU Design Engineering Manager
Intel GmbH, San Jose, California, United States, 95199
Job Description
In Q4 2023, Intel announced Altera will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel . This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future. Altera designs and manufactures FPGAs for a wide range of applications. The successful incumbent in this role
will manage an FPGA design team to design
CPU subsystems that are used by customers to run workloads and program other IPs. The CPU subsystems
team
design s
and implements a wide range of IPs including CPUs and interconnects. You
will manage
a growing team of 10 and is primarily located in San Jose, Oregan and Austin.The successful incumbent in this position will perform the following but not limited to:Leads and manages CPU silicon design teams within one or more areas of functional development including logic design, verification, circuit design, and/or physical design for a CPU.
Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards.
Takes active part in defining CPU microarchitectural features and drives their implementation.
Conducts design reviews to ensure key factors such as power, performance, area, and cost are meeting requirements.
Works to continuously to improve CPU silicon development processes and architecture definition across areas of CPU silicon design.
Oversees and reviews design verification test results, data analysis, issue tracking, root cause analysis, and drives corrective actions implementation for silicon design.
Works closely across other IP and SoC development teams that integrate the CPU to design complex projects, ensure quality, drive performance, and design implementation.
Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.
Provide daily technical guidance to the team to implement designs in RTL and execute design flow to tape out designs to meet schedules.
Resolve conflicts
Manage the design team in cross functional meetings, prepare team status, manage hiring
Qualifications
Education RequirementsB.SC. electrical engineering or related field.Minimum Qualifications10+ years of experience in the following:
CPU architecture and design for ARM and CPU
subsystems
including cache architecture and coherency.
Programming model of peripheral IPs such as USB, Ethernet, I3C, PCIe.
Coherent and non-coherent Network-on-Chip architecture and design
CPU subsystems integration challenges and tradeoffs for power, performance and area
Preferred QualificationsMaster’s Degree with 6+ year or PHD with 4+ years in electrical engineering or related field6+ years of experience in any of the following:ASIC flow from RTL to GDSII with
Synthesis, place and route, physical implementation,
Constraint design, timing closure,
DRC/LVS, DFT, DFD, memory designs, clock
Reset circuits, low power modes, packaging tradeoffs
Inside this Business Group The Programmable Solutions Group (PSG) was formed from the acquisition of Altera.
As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency.
PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation.
We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees.
That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits
here.Annual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.#J-18808-Ljbffr
In Q4 2023, Intel announced Altera will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel . This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future. Altera designs and manufactures FPGAs for a wide range of applications. The successful incumbent in this role
will manage an FPGA design team to design
CPU subsystems that are used by customers to run workloads and program other IPs. The CPU subsystems
team
design s
and implements a wide range of IPs including CPUs and interconnects. You
will manage
a growing team of 10 and is primarily located in San Jose, Oregan and Austin.The successful incumbent in this position will perform the following but not limited to:Leads and manages CPU silicon design teams within one or more areas of functional development including logic design, verification, circuit design, and/or physical design for a CPU.
Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards.
Takes active part in defining CPU microarchitectural features and drives their implementation.
Conducts design reviews to ensure key factors such as power, performance, area, and cost are meeting requirements.
Works to continuously to improve CPU silicon development processes and architecture definition across areas of CPU silicon design.
Oversees and reviews design verification test results, data analysis, issue tracking, root cause analysis, and drives corrective actions implementation for silicon design.
Works closely across other IP and SoC development teams that integrate the CPU to design complex projects, ensure quality, drive performance, and design implementation.
Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.
Provide daily technical guidance to the team to implement designs in RTL and execute design flow to tape out designs to meet schedules.
Resolve conflicts
Manage the design team in cross functional meetings, prepare team status, manage hiring
Qualifications
Education RequirementsB.SC. electrical engineering or related field.Minimum Qualifications10+ years of experience in the following:
CPU architecture and design for ARM and CPU
subsystems
including cache architecture and coherency.
Programming model of peripheral IPs such as USB, Ethernet, I3C, PCIe.
Coherent and non-coherent Network-on-Chip architecture and design
CPU subsystems integration challenges and tradeoffs for power, performance and area
Preferred QualificationsMaster’s Degree with 6+ year or PHD with 4+ years in electrical engineering or related field6+ years of experience in any of the following:ASIC flow from RTL to GDSII with
Synthesis, place and route, physical implementation,
Constraint design, timing closure,
DRC/LVS, DFT, DFD, memory designs, clock
Reset circuits, low power modes, packaging tradeoffs
Inside this Business Group The Programmable Solutions Group (PSG) was formed from the acquisition of Altera.
As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency.
PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation.
We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees.
That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits
here.Annual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.#J-18808-Ljbffr