Sanmina-SCI Systems de México
Principal Microelectronics Engineer
Sanmina-SCI Systems de México, Costa Mesa, California, United States, 92626
Job Purpose:
Candidate will lead the design and development of innovative microelectronics packaging solutions for high density memory products targeted at the defense, aerospace, and commercial markets.
Nature of Duties/Responsibilities:
Lead a team of engineers and subcontractors in the development and qualification of DRAM and Flash products including multichip modules (MCM), plastic ball grid array multichip packages (MCP), and System-In-Package (SiP) solutions.
Responsible for project scheduling and execution, project status reporting, and providing technical guidance to the team.
Interface directly with onshore and offshore assembly and test subcontractors (OSAT) and OEM customers.
Some travel may be required.
Education and Experience:
Minimum 10-12 years related experience.
BS in Microelectronics Packaging, EE, Mechanical Engineering, Physics, or Materials.
Experience in the design of semiconductor packages such as plastic ball grid arrays, MultiChip Packages (MCPs), and System-in-Package (SiP).
Solid understanding of semiconductor package design parameters and their influence on cost, thermal and electrical performance, reliability, and manufacturability.
Experience leading cross-functional engineering teams in complex microelectronics packaging projects.
Project management experience including scheduling, status reporting, and subcontractor management.
Thorough understanding of microelectronics package design flow, including mechanical design, signal integrity simulation, thermal simulation, schematic capture, and PCB layout.
Thorough understanding of high volume manufacturing processes for semiconductor ICs (backend packaging and test).
Familiarity with silicon wafer post-process techniques such as wafer thinning, dicing, and RDL application.
Thorough understanding and experience in packaging qualification testing techniques and industry standard test methods.
Experience interfacing directly with onshore and offshore microelectronics assembly and test subcontractors (OSAT).
Experience with printed circuit board assembly, SMT processing equipment and methods.
Familiarity with integrated circuit functional test and burn in techniques.
Excellent verbal and written communication skills.
PACKAGING Skills:
Wafer level packaging, Wafer preparation (dicing, grinding, wafer expansion, die singulation).
Die pick and place, Die Attach, Die Stack, MEMS die, FLIP CHIP, Underfill, Thermo-compression bonding, WIREBOND, Molding (transfer mold).
Compression mold, vacuum mold, film-assist mold, Dam and Fill dispense, Ball Attach, Solder Reflow, Singulation, Tape and Reel, SMT (Surface Mount Technology).
Packages handled and developed: QFP, TQFP, SOP, TSOP, QFN, Flip Chip, Cu pillar FC, BGA, CSP, FAN-OUT WAFER LEVEL PACKAGING (FOWLP), 2.5DIC, 3DIC, Thru mold vias, Thru-silicon.
Sanmina is an Equal Opportunity Employer – M/F/Veteran/Disability/Sexual Orientation/Gender Identity.
This is an ITAR facility. Must be US Citizen or lawful permanent resident.
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Candidate will lead the design and development of innovative microelectronics packaging solutions for high density memory products targeted at the defense, aerospace, and commercial markets.
Nature of Duties/Responsibilities:
Lead a team of engineers and subcontractors in the development and qualification of DRAM and Flash products including multichip modules (MCM), plastic ball grid array multichip packages (MCP), and System-In-Package (SiP) solutions.
Responsible for project scheduling and execution, project status reporting, and providing technical guidance to the team.
Interface directly with onshore and offshore assembly and test subcontractors (OSAT) and OEM customers.
Some travel may be required.
Education and Experience:
Minimum 10-12 years related experience.
BS in Microelectronics Packaging, EE, Mechanical Engineering, Physics, or Materials.
Experience in the design of semiconductor packages such as plastic ball grid arrays, MultiChip Packages (MCPs), and System-in-Package (SiP).
Solid understanding of semiconductor package design parameters and their influence on cost, thermal and electrical performance, reliability, and manufacturability.
Experience leading cross-functional engineering teams in complex microelectronics packaging projects.
Project management experience including scheduling, status reporting, and subcontractor management.
Thorough understanding of microelectronics package design flow, including mechanical design, signal integrity simulation, thermal simulation, schematic capture, and PCB layout.
Thorough understanding of high volume manufacturing processes for semiconductor ICs (backend packaging and test).
Familiarity with silicon wafer post-process techniques such as wafer thinning, dicing, and RDL application.
Thorough understanding and experience in packaging qualification testing techniques and industry standard test methods.
Experience interfacing directly with onshore and offshore microelectronics assembly and test subcontractors (OSAT).
Experience with printed circuit board assembly, SMT processing equipment and methods.
Familiarity with integrated circuit functional test and burn in techniques.
Excellent verbal and written communication skills.
PACKAGING Skills:
Wafer level packaging, Wafer preparation (dicing, grinding, wafer expansion, die singulation).
Die pick and place, Die Attach, Die Stack, MEMS die, FLIP CHIP, Underfill, Thermo-compression bonding, WIREBOND, Molding (transfer mold).
Compression mold, vacuum mold, film-assist mold, Dam and Fill dispense, Ball Attach, Solder Reflow, Singulation, Tape and Reel, SMT (Surface Mount Technology).
Packages handled and developed: QFP, TQFP, SOP, TSOP, QFN, Flip Chip, Cu pillar FC, BGA, CSP, FAN-OUT WAFER LEVEL PACKAGING (FOWLP), 2.5DIC, 3DIC, Thru mold vias, Thru-silicon.
Sanmina is an Equal Opportunity Employer – M/F/Veteran/Disability/Sexual Orientation/Gender Identity.
This is an ITAR facility. Must be US Citizen or lawful permanent resident.
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