Kolar Design, Inc.
Sr Staff/Principal FPGA Design Engineer
Kolar Design, Inc., Palo Alto, California, United States, 94306
Array Labs is building a distributed radar imaging constellation to power the first accurate, real-time 3D model of the world.
The Hardware Engineering team at Array Labs is responsible for the analysis and design of our satellite and ground-station hardware platforms. These platforms tend to be a heterogeneous mix of various subsystems like compute, memory, peripherals with high-speed interfaces, RF, sensing, power management, navigation, and controls. The focus areas of the Hardware Engineering Team can be split into Aerospace/Avionics, Electrical/Electronics (EE) and Communications/Radar engineering. As an FPGA Design Engineer in the Hardware Engineering team, you will create solutions on our FPGA platform to support Array Lab’s radar and communications payload as well as our ground infrastructure. You will work with Communication Systems and Radar Algorithms teams to define, implement, and test various algorithms, control systems, and modem systems on our FPGA platform. The role requires implementing proprietary algorithms and integrating third-party IPs on the FPGA platform. This is a unique opportunity to join our early team and make a significant impact by contributing to the creation of a brand-new platform free from any legacy limitations.
Responsibilities:
Collaborate with Radar, Communications, and RF engineers to define, implement, and test various signal processing algorithms and digital logic functions in FPGAsWork with HW Design Engineers and Embedded SW engineers to rapidly prototype and bring up satellite payloads that combine FPGA, processors, firmware, sensors, and networking functionalityTake full responsibility for executing RTL design with or without HLS (High-Level Synthesis), physical implementation, timing closure, and validation through simulationCreate robust software infrastructure using modern coding techniques to ensure that FPGA images seamlessly integrate into our hardware platform's Board Support Package while also functioning independentlyBasic Qualifications:
B.S in Electrical or Computer Engineering11+ years of experience in modern FPGA design, implementation, and verificationSolid understanding of FPGA logic Synthesis, partitioning, routing and timing closureExcellent teamwork and communication skillsLearns new concepts rapidly, completely, and in a self-directed mannerHigh levels of self-motivation and personal accountabilityAbility to work in a fast-paced environment under significant time constraintsExperience in FPGA or ASIC design in VHDL, Verilog, or SystemVerilogExperience with FPGA tools, preferably Xilinx VivadoPreferred Skills and Experience:
Master's degree in Electrical or Computer Engineering6+ years of FPGA prototyping experience (compilation, debugging and throughput tuning) on Xilinx/Altera/Lattice Semiconductor FGPAsStrong logic design, RTL coding (Verilog / VHDL), and debugging skillsFamiliar with design constraints, logic synthesis, timing closure analysis, and clock/reset domain crossing checksProficiency with FPGA synthesis and implementation tools (e.g. Xilinx Vivado, Altera Quartus II), HDL simulators (VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), and Power Analysis tools.Experience implementing fixed-point DSP blocks in RTL, such as IIR and FIR filters, modulator/demodulator, encoder/decoders PLLs, CORDIC operations and FFT processors, and CORDIC processorsFamiliarity with custom IP verification and integrationExperience creating UVM-based test benches for verification of FPGA designsFamiliarity with processor architecture and associated communications protocols such as AXI, DMA, I2C, UART, SPI, PCIE, USB, and Ethernet.Proficiency in scripting languages such as Python and BashExperience with high-speed SERDES interfaces, Ethernet, and IP networkingITAR Requirements:
To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.Equal Opportunity Employer
Array Labs is an Equal Opportunity Employer. Employment decisions are made on the basis of merit, competence, and job qualifications and will not be influenced in any manner by gender, color, race, ethnicity, national origin, sexual orientation, religion, age, gender identity, veteran status, disability status, marital status, mental or physical disability or any other legally protected status.
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The Hardware Engineering team at Array Labs is responsible for the analysis and design of our satellite and ground-station hardware platforms. These platforms tend to be a heterogeneous mix of various subsystems like compute, memory, peripherals with high-speed interfaces, RF, sensing, power management, navigation, and controls. The focus areas of the Hardware Engineering Team can be split into Aerospace/Avionics, Electrical/Electronics (EE) and Communications/Radar engineering. As an FPGA Design Engineer in the Hardware Engineering team, you will create solutions on our FPGA platform to support Array Lab’s radar and communications payload as well as our ground infrastructure. You will work with Communication Systems and Radar Algorithms teams to define, implement, and test various algorithms, control systems, and modem systems on our FPGA platform. The role requires implementing proprietary algorithms and integrating third-party IPs on the FPGA platform. This is a unique opportunity to join our early team and make a significant impact by contributing to the creation of a brand-new platform free from any legacy limitations.
Responsibilities:
Collaborate with Radar, Communications, and RF engineers to define, implement, and test various signal processing algorithms and digital logic functions in FPGAsWork with HW Design Engineers and Embedded SW engineers to rapidly prototype and bring up satellite payloads that combine FPGA, processors, firmware, sensors, and networking functionalityTake full responsibility for executing RTL design with or without HLS (High-Level Synthesis), physical implementation, timing closure, and validation through simulationCreate robust software infrastructure using modern coding techniques to ensure that FPGA images seamlessly integrate into our hardware platform's Board Support Package while also functioning independentlyBasic Qualifications:
B.S in Electrical or Computer Engineering11+ years of experience in modern FPGA design, implementation, and verificationSolid understanding of FPGA logic Synthesis, partitioning, routing and timing closureExcellent teamwork and communication skillsLearns new concepts rapidly, completely, and in a self-directed mannerHigh levels of self-motivation and personal accountabilityAbility to work in a fast-paced environment under significant time constraintsExperience in FPGA or ASIC design in VHDL, Verilog, or SystemVerilogExperience with FPGA tools, preferably Xilinx VivadoPreferred Skills and Experience:
Master's degree in Electrical or Computer Engineering6+ years of FPGA prototyping experience (compilation, debugging and throughput tuning) on Xilinx/Altera/Lattice Semiconductor FGPAsStrong logic design, RTL coding (Verilog / VHDL), and debugging skillsFamiliar with design constraints, logic synthesis, timing closure analysis, and clock/reset domain crossing checksProficiency with FPGA synthesis and implementation tools (e.g. Xilinx Vivado, Altera Quartus II), HDL simulators (VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), and Power Analysis tools.Experience implementing fixed-point DSP blocks in RTL, such as IIR and FIR filters, modulator/demodulator, encoder/decoders PLLs, CORDIC operations and FFT processors, and CORDIC processorsFamiliarity with custom IP verification and integrationExperience creating UVM-based test benches for verification of FPGA designsFamiliarity with processor architecture and associated communications protocols such as AXI, DMA, I2C, UART, SPI, PCIE, USB, and Ethernet.Proficiency in scripting languages such as Python and BashExperience with high-speed SERDES interfaces, Ethernet, and IP networkingITAR Requirements:
To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.Equal Opportunity Employer
Array Labs is an Equal Opportunity Employer. Employment decisions are made on the basis of merit, competence, and job qualifications and will not be influenced in any manner by gender, color, race, ethnicity, national origin, sexual orientation, religion, age, gender identity, veteran status, disability status, marital status, mental or physical disability or any other legally protected status.
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