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Synopsys

R&D Engineering, Sr Architect

Synopsys, Mountain View, California, us, 94039


R&D Engineering, Sr Architect

51267BRUSA - California - Mountain View/SunnyvaleJob Description and RequirementsWe're looking for a senior DDR/HBM PHY architect to join the team. In this position, you would be part of a team that plans and executes the design for the next-generation DDR and HBM PHYs in the Synopsys IP portfolio. The job entails understanding industry trends through participation in standards bodies, evaluating ideas, drafting specifications, and enabling the design team to put your ideas into silicon. You'd leverage your understanding of computer architecture, mixed-signal design, off-chip signaling, RTL development, design-for-test, and logical verification to create leading-edge products. Supporting Synopsys' customers is also a significant part of the role. You will join a collaborative, multi-person engineering team engaged in similar activities on related DDR and HBM PHY development projects.Job Responsibilities:Understands marketing and customer desires for Synopsys' DDR and HBM PHY interface performance and functionalityTranslates those desires into a set of product design features and functionsGenerates the functional description for the product, creating specifications describing the interface components, operation, structure, and behavioral parametersOptimizes the design for performance, power, and areaInteracts and communicates with design teams performing logical design, logical verification, analog circuit design and verification, and layout designSupports customers in their implementation of the productTracks industry developments through standards committees, representing Synopsys in these committeesKey Qualifications and Experience:Understands high-speed interface principles, such as mixed-signal design and off-chip signalingSkilled in generating and supporting documentation through written specifications, and communicating those specifications within a design team and to external customersWell-versed in RTL logic design, simulation, test planning, and verification of complex integrated circuit componentsKnowledgeable in design-for-test, timing analysis, power analysis, behavioral modeling, and synthesis constraintsAble to work across a multi-site team to communicate ideas, understand problems, and find solutions to create a leading-edge designSkilled in troubleshooting and debug of mixed-signal interfacesPossesses a minimum of 12 years of related experienceThe base salary range across the U.S. for this role is between $199,000-$299,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.Job Category: EngineeringCountry: United StatesJob Subcategory: R&D EngineeringHire Type: EmployeeBase Salary Range: $199,000 - $299,000

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