CV Library
Analog IC Layout Engineer
CV Library, San Diego, California, United States, 92189
Elevate Semiconductor’s mission is to serve our semiconductor and system test customers by providing world class test integrated circuits (ICs) that address the industry’s most complex ATE challenges. We strive to exceed our customer’s expectations, now and well into the future, through designing the lowest power/highest density solutions, with the goal of providing the lowest possible cost of test.
As an Analog IC Layout Engineer, you will work with a small team to develop leading edge ATE integrated circuits. You will handle the physical layout and verification of very complex and highly integrated solutions on leading edge high voltage and mixed voltage/mixed gate process technologies encompassing 65nm CMOS to 100+V BCD with the support and mentorship from Senior Engineers.
Responsibilities
Floorplanning, layout, verification of circuits.Partner with Analog IC design, Digital PnR, Package design to effectively optimize silicon area and usage to reduce costs and increase performance.
Requirements
Bachelors degree in Electrical Engineering.Solid analog CMOS circuit and device physics fundamentals.Understanding of the IC design, qualification and manufacturing cycle.Experience with industry standard analog and mixed signal EDA tools (Cadence/Mentor Graphics/Tanner). LVS and DRC using Cadence or Mentor tools.Must be able to work onsite in San Diego, CA.
Preferences
Layout experience with STI High voltage (100V+) BCD and LDMOS processes.Layout experience with mixed voltage (multiple supply rails, 6 or more) domains.Layout experience with high speed multi Gbps circuits.Layout experience in ultra-high accuracy and precision circuits.Layout experience with high resolution data converters.Layout experience with BiCMOS process technology.Programming and scripting ability a strong plus, particularly in SKILL and Calibre scripts.
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As an Analog IC Layout Engineer, you will work with a small team to develop leading edge ATE integrated circuits. You will handle the physical layout and verification of very complex and highly integrated solutions on leading edge high voltage and mixed voltage/mixed gate process technologies encompassing 65nm CMOS to 100+V BCD with the support and mentorship from Senior Engineers.
Responsibilities
Floorplanning, layout, verification of circuits.Partner with Analog IC design, Digital PnR, Package design to effectively optimize silicon area and usage to reduce costs and increase performance.
Requirements
Bachelors degree in Electrical Engineering.Solid analog CMOS circuit and device physics fundamentals.Understanding of the IC design, qualification and manufacturing cycle.Experience with industry standard analog and mixed signal EDA tools (Cadence/Mentor Graphics/Tanner). LVS and DRC using Cadence or Mentor tools.Must be able to work onsite in San Diego, CA.
Preferences
Layout experience with STI High voltage (100V+) BCD and LDMOS processes.Layout experience with mixed voltage (multiple supply rails, 6 or more) domains.Layout experience with high speed multi Gbps circuits.Layout experience in ultra-high accuracy and precision circuits.Layout experience with high resolution data converters.Layout experience with BiCMOS process technology.Programming and scripting ability a strong plus, particularly in SKILL and Calibre scripts.
#J-18808-Ljbffr